openpower/sv/cr_ops.mdwn

   1 # Condition Register SVP64 Operations
   2
   3 Links:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
   6
   7 Condition Register Fields are only 4 bits wide: this presents some
   8 interesting conceptual challenges for SVP64, particularly with respect to element
   9 width (which is clearly meaningless for a 4-bit
  10 collation of Conditions, EQ LT GE SO). Likewise, arithmetic saturation
  11 (an important part of Arithmetic SVP64)
  12 has no meaning. Additionally, extra modes are required that only make
  13 sense for Vectorised CR Operations. Consequently an alternative Mode Format is required.
  14
  15 This alternative mapping **only** applies to instructions that **only**
  16 reference a CR Field or CR bit as the sole exclusive result. This section
  17 **does not** apply to instructions which primarily produce arithmetic
  18 results that also, as an aside, produce a corresponding
  19 CR Field (such as when Rc=1).
  20 Instructions that involve Rc=1 are definitively arithmetic in nature,
  21 where the corresponding Condition Register Field can be considered to
  22 be a "co-result". Such CR Field "co-result" arithmeric operations
  23 are firmly out of scope for
  24 this section.
  25
  26 * Examples of v3.0B instructions to which this section does
  27   apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands).
  28 * Examples to which this section does **not** apply include
  29   `fadds.` and `subf.` which both produce arithmetic results
  30   (and a CR Field co-result).
  31
  32 Other modes are still applicable and include:
  33
  34 * **Data-dependent fail-first**.
  35   useful to truncate VL based on
  36   analysis of a Condition Register result bit.
  37 * **Scalar and parallel reduction**.
  38   Reduction is useful
  39 for turning a Vector of Condition Register Fields into one
  40 single Condition Register.
  41 * **Predicate-result**.
  42   Equivalent
  43 to python "filter", in that only elements which pass a test
  44 will end up actually being modified. This is in effect the same
  45 as ANDing the Condition Test with the destination predicate
  46 mask (hence the name, "predicate-result").
  47
  48 Predicate-result is a particularly powerful strategic mode
  49 in that it is the interaction of a source predicate, destination predicate,
  50 input operands *and* the output result, all combining to influence
  51 what actually goes into the Condition Register File. Given that
  52 predicates may themselves be Condition Registers it can be seen that
  53 there could potentially be up to **six** CR Fields involved in
  54 the execution of Predicate-result Mode.
  55
  56 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  57
  58 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  59 | - | - | ----- | --- |---------|----------------- |
  60 | / | / | 00    |   0 |  dz  sz | normal mode                      |
  61 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  62 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
  63 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  64 |dz |VLi| 01    | inv |  CR-bit | Ffirst 3-bit mode      |
  65 |sz |VLi| 01    | inv |  dz Rc1 | Ffirst 5-bit mode       |
  66 | / | / | 10    |   / | /   /   |  RESERVED |
  67 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |
  68 | / |SNZ| 11    | inv | dz  sz  |  5-bit pred-result z/nonz |
  69
  70 Fields:
  71
  72 TODO
  73
  74 # Data-dependent fail-first on CR operations
  75
  76 The principle of data-dependent fail-first is that if a Condition Test
  77 fails then VL (Vector Length) is truncated at that point. In the case
  78 of Arithmetic SVP64 Operations the Condition Register Field generated from
  79 Rc=1 is used, however with CR-based operations that CR result is provided
  80 by the operation itself.
  81
  82 Data-dependent SVP64 Vectorised Operations involving the creation or
  83 modification of a CR can require an extra two bits, which are not available
  84 in the compact space of the SVP64 RM `MODE` Field. With the concept of element
  85 width overrides being meaningless for CR Fields it is possible to use the
  86 `ELWIDTH` field for alternative purposes.
  87
  88 Condition Register based operations such as `sv.mfcr` and `sv.crand` can thus
  89 be made more flexible.  However the rules that apply in this section
  90 also apply to future CR-based instructions.
  91
  92 There are two primary different types of CR operations:
  93
  94 * Those which have a 3-bit operand field (referring to a CR Field)
  95 * Those which have a 5-bit operand (referring to a bit within the
  96    whole 32-bit CR)
  97
  98 Examining these two types it is observed that the
  99 difference may be considered to be that the 5-bit variant provides
 100 additional information about which CR Field bit (EQ, GE, LT, SO) is to
 101 be operated on by the instruction.
 102 Thus, logically, we may set the following rule:
 103
 104 * When a 5-bit CR Result field is used in an instruction, the
 105   5-bit variant of Data-Dependent Fail-First
 106   must be used. i.e. the bit of the CR field to be tested is
 107   the one that has just been modified (created) by the operation.
 108 * When a 3-bit CR Result field is used the 3-bit variant
 109   must be used, providing as it does the missing `CRbit`
 110   in order to select which CR Field bit of the result shall
 111   be tested (EQ, LE, GE, SO)
 112
 113 The reason why the 3-bit CR variant needs the additional CR-bit
 114 field should be obvious from the fact that the 3-bit CR Field
 115 from the base Power ISA v3.0B operation clearly does not contain
 116 and is missing the two CR Field Selector bits. Thus, these two
 117 bits (to select EQ, LE, GE or SO) must be provided in another
 118 way.
 119
 120 Examples of the former type:
 121
 122 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
 123   to be tested against `inv` is the one selected by `BT`
 124 * mcrf. This has only 3-bit (BF, BFA). In order to select the
 125   bit to be tested, the alternative encoding must be used.
 126   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
 127   of BF to be tested is identified.
 128
 129 # Predicate-result Condition Register operations
 130
 131 These are again slightly different compared to SVP64 arithmetic
 132 pred-result (described in [[svp64/appendix]]). The reason is that,
 133 again, for arithmetic operations the production of a CR Field when
 134 Rc=1 is a *co-result* accompanying the main arithmetic result, whereas
 135 for CR-based operations the CR Field (referred to by a 3-bit
 136 v3.0B base operand from e.g. `mfcr`) or CR bit (referred to by a 5-bit operand from e.g. `crnor`)
 137 *is* itself the explicit and sole result of the operation.
 138
 139 Therefore, logically, Predicate-result needs to be adapted to
 140 test the actual result of the CR-based instruction, rather than
 141 test the co-resultant CR when Rc=1.
 142
 143     for i in range(VL):
 144         # predication test, skip all masked out elements.
 145         # skips when sz=0
 146         if sz=0 and predicate_masked_out(i):
 147              continue
 148         if predicate_masked_out(i):
 149            if 5bit mode:
 150               # only one bit of CR to update
 151               result = SNZ
 152            else
 153               # four copies of SNZ
 154               result = SNZ || SNZ || SNZ || SNZ
 155         else
 156            # result is to go into CR. may be a 4-bit CR Field
 157            # (3-bit mode) or just a single bit (5-bit mode)
 158            result = op(...)
 159         if 5bit mode:
 160            # if this CR op has 5-bit CR result operands
 161            # the single bit result is what must be tested
 162            to_test = result
 163         else
 164            # if however this is a 3-bit CR *field* result
 165            # then the bit to be tested must be selected
 166            to_test = result[CRbit]
 167         # now test CR, similar to branch
 168         if to_test != inv:
 169             continue # test failed: cancel store
 170         # result optionally stored
 171         update_CR(result)