openpower/sv/cr_ops.mdwn

   1 # Data-dependent fail-first on CR operations
   2
   3 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
   4
   5 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
   6 | - | - | ----- | --- |---------|----------------- |
   7 |dz |VLi| 01    | inv |  CR-bit | normal mode      |
   8 |sz |VLi| 01    | inv |  dz Rc1 | VLSET mode       |
   9
  10 Operations that actually produce or alter CR Field as a result
  11 do not also in turn have an Rc=1 mode.  However it makes no
  12 sense to try to test the 4 bits of a CR Field for being equal
  13 or not equal to zero. Moreover, the result is already in the
  14 form that is desired: it is a CR field.
  15
  16 There are two primary different types of CR operations:
  17
  18 * Those which have a 3-bit operand field (referring to a CR Field)
  19 * Those which have a 5-bit operand (referring to a bit within the
  20    whole 32-bit CR)
  21
  22 Examining these two as has already been done it is observed that
  23 the difference may be considered to be that the 5-bit variant
  24 provides additional information about which CR Field bit
  25 (EQ, GE, LT, SO) is to be operated on by the instruction.
  26
  27 Thus, logically, we may set the following rule:
  28
  29 * When a 5-bit CR Result field is used in an instruction, the
  30   `inv, VLi and RC1` variant of Data-Dependent Fail-First
  31   must be used. i.e. the bit of the CR field to be tested is
  32   the one that has just been modified by the operation.
  33 * When a 3-bit CR Result field is used the `inv CRbit` variant
  34   must be used in order to select which CR Field bit shall
  35   be tested (EQ, LE, GE, SO).
  36
  37 Examples of the former type:
  38
  39 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
  40   to be tested against `inv` is the one selected by `BT`
  41 * mcrf. This has only 3-bit (BF, BFA). In order to select the
  42   bit to be tested, the alternative FFirst encoding must be used.
  43
  44 This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
  45 Mode. This is unfortunste but unavoidable due to encoding pressure
  46 on SVP64.
  47