openpower/sv/cr_ops.mdwn

   1 # Condition Register SVP64 Operations
   2
   3 Condition Register Fields are only 4 bits wide: this presents some
   4 interesting conceptual challenges for SVP64, oarticularly with respect to element
   5 width (which is clearly meaningless). Likewise, arithmetic saturation
   6 has no meaning. Consequently an alternative Mode Format is required.
   7
   8 This alternative mapping **only** applies to instructions that **only**
   9 reference a CR Field or CR bit as the sole exclusive result. This section
  10 **does not** apply to instructions which primarily produce arithmetic
  11 results that also produce a CR Field (such as when Rc=1).
  12 Instructions that involve Rc=1 are definitively arithmetic in nature,
  13 where the corresponding Condition Register Field can be considered to
  14 be a "co-result". Thus, if the arithmetic result is Vectorised, so
  15 is the CR Field "co-result", which puts both firmly out of scope for
  16 this section.
  17
  18 Other modes are still applicable and include:
  19
  20 * Data-dependent fail-first
  21 * Scalar and parallel reduction
  22 * Predicate-result
  23
  24 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  25
  26 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  27 | - | - | ----- | --- |---------|----------------- |
  28 |dz |VLi| 01    | inv |  CR-bit | Ffirst 3-bit mode      |
  29 |sz |VLi| 01    | inv |  dz Rc1 | Ffirst 5-bit mode       |
  30 | / | / | 00    |   0 |  dz  sz | normal mode                      |
  31 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  32 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
  33 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  34 | / | / | 10    |   / | /   /   |  RESERVED |
  35 |dz | / | 11    | inv | CR-bit  |  3-bit pred-result CR sel |
  36 |sz | / | 11    | inv | dz  RC1 |  5-bit pred-result z/nonz |
  37
  38 Fields:
  39
  40
  41 # Data-dependent fail-first and Pred-result on CR operations
  42
  43 Data-dependent SVP64 Vectorised Operations involving the creation or
  44 modification of a CR require an extra two bits, which are not available
  45 in the compact space of the `MODE` Field. With the concept of element
  46 width overrides being meaningless for CR Fields it is possible to use the
  47 `ELWIDTH` field for extra fields.
  48
  49 Condition Register based operations such as `mfcr` and `crand` can thus
  50 be made more flexible.  However the rules that apply in this section
  51 also apply to future CR-based instructions.
  52
  53 There are two primary different types of CR operations:
  54
  55 * Those which have a 3-bit operand field (referring to a CR Field)
  56 * Those which have a 5-bit operand (referring to a bit within the
  57    whole 32-bit CR)
  58
  59 Examining these two as has already been done it is observed that the
  60 difference may be considered to be that the 5-bit variant provides
  61 additional information about which CR Field bit (EQ, GE, LT, SO) is to
  62 be operated on by the instruction.
  63
  64 Thus, logically, we may set the following rule:
  65
  66 * When a 5-bit CR Result field is used in an instruction, the
  67   `inv, VLi and RC1` variant of Data-Dependent Fail-First
  68   must be used. i.e. the bit of the CR field to be tested is
  69   the one that has just been modified by the operation.
  70 * When a 3-bit CR Result field is used the `inv CRbit` variant
  71   must be used in order to select which CR Field bit shall
  72   be tested (EQ, LE, GE, SO)
  73
  74 The reason why the 3-bit CR variant needs the additional CR-bit
  75 field should be obvious from the fact that the 3-bit CR Field
  76 from the base Power ISA v3.0B operation clearly does not contain
  77 and is missing the two CR Field Selector bits. Thus, these two
  78 bits (to select EQ, LE, GE or SO) must be provided in another
  79 way.
  80
  81 Examples of the former type:
  82
  83 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
  84   to be tested against `inv` is the one selected by `BT`
  85 * mcrf. This has only 3-bit (BF, BFA). In order to select the
  86   bit to be tested, the alternative FFirst encoding must be used.
  87
  88 This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
  89 Mode. This is unfortunste but unavoidable due to encoding pressure
  90 on SVP64.
  91