openpower/sv/cr_ops.mdwn

   1 # Condition Register SVP64 Operations
   2
   3 Condition Register Fields are only 4 bits wide: this presents some
   4 interesting conceptual challenges for SVP64, particularly with respect to element
   5 width (which is clearly meaningless). Likewise, arithmetic saturation
   6 (an important part of Arithmetic SVP64)
   7 has no meaning. Consequently an alternative Mode Format is required.
   8
   9 This alternative mapping **only** applies to instructions that **only**
  10 reference a CR Field or CR bit as the sole exclusive result. This section
  11 **does not** apply to instructions which primarily produce arithmetic
  12 results that also produce a CR Field (such as when Rc=1).
  13 Instructions that involve Rc=1 are definitively arithmetic in nature,
  14 where the corresponding Condition Register Field can be considered to
  15 be a "co-result". Thus, if the arithmetic result is Vectorised, so
  16 is the CR Field "co-result", which puts both firmly out of scope for
  17 this section.
  18
  19 Other modes are still applicable and include:
  20
  21 * Data-dependent fail-first
  22 * Scalar and parallel reduction
  23 * Predicate-result
  24
  25 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  26
  27 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  28 | - | - | ----- | --- |---------|----------------- |
  29 |dz |VLi| 01    | inv |  CR-bit | Ffirst 3-bit mode      |
  30 |sz |VLi| 01    | inv |  dz Rc1 | Ffirst 5-bit mode       |
  31 | / | / | 00    |   0 |  dz  sz | normal mode                      |
  32 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  33 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
  34 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  35 | / | / | 10    |   / | /   /   |  RESERVED |
  36 |dz | / | 11    | inv | CR-bit  |  3-bit pred-result CR sel |
  37 |sz | / | 11    | inv | dz  RC1 |  5-bit pred-result z/nonz |
  38
  39 Fields:
  40
  41
  42 # Data-dependent fail-first and Pred-result on CR operations
  43
  44 Data-dependent SVP64 Vectorised Operations involving the creation or
  45 modification of a CR require an extra two bits, which are not available
  46 in the compact space of the `MODE` Field. With the concept of element
  47 width overrides being meaningless for CR Fields it is possible to use the
  48 `ELWIDTH` field for extra fields.
  49
  50 Condition Register based operations such as `mfcr` and `crand` can thus
  51 be made more flexible.  However the rules that apply in this section
  52 also apply to future CR-based instructions.
  53
  54 There are two primary different types of CR operations:
  55
  56 * Those which have a 3-bit operand field (referring to a CR Field)
  57 * Those which have a 5-bit operand (referring to a bit within the
  58    whole 32-bit CR)
  59
  60 Examining these two as has already been done it is observed that the
  61 difference may be considered to be that the 5-bit variant provides
  62 additional information about which CR Field bit (EQ, GE, LT, SO) is to
  63 be operated on by the instruction.
  64
  65 Thus, logically, we may set the following rule:
  66
  67 * When a 5-bit CR Result field is used in an instruction, the
  68   `inv, VLi and RC1` variant of Data-Dependent Fail-First
  69   must be used. i.e. the bit of the CR field to be tested is
  70   the one that has just been modified by the operation.
  71 * When a 3-bit CR Result field is used the `inv CRbit` variant
  72   must be used in order to select which CR Field bit shall
  73   be tested (EQ, LE, GE, SO)
  74
  75 The reason why the 3-bit CR variant needs the additional CR-bit
  76 field should be obvious from the fact that the 3-bit CR Field
  77 from the base Power ISA v3.0B operation clearly does not contain
  78 and is missing the two CR Field Selector bits. Thus, these two
  79 bits (to select EQ, LE, GE or SO) must be provided in another
  80 way.
  81
  82 Examples of the former type:
  83
  84 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
  85   to be tested against `inv` is the one selected by `BT`
  86 * mcrf. This has only 3-bit (BF, BFA). In order to select the
  87   bit to be tested, the alternative FFirst encoding must be used.
  88
  89 This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
  90 Mode. This is unfortunste but unavoidable due to encoding pressure
  91 on SVP64.
  92