openpower/sv/cr_ops.mdwn

   1 # Condition Register SVP64 Operations
   2
   3 Condition Register Fields are only 4 bits wide: this presents some
   4 interesting conceptual challenges for SVP64, particularly with respect to element
   5 width (which is clearly meaningless). Likewise, arithmetic saturation
   6 (an important part of Arithmetic SVP64)
   7 has no meaning. Consequently an alternative Mode Format is required.
   8
   9 This alternative mapping **only** applies to instructions that **only**
  10 reference a CR Field or CR bit as the sole exclusive result. This section
  11 **does not** apply to instructions which primarily produce arithmetic
  12 results that also, as an aside, produce a corresponding
  13 CR Field (such as when Rc=1).
  14 Instructions that involve Rc=1 are definitively arithmetic in nature,
  15 where the corresponding Condition Register Field can be considered to
  16 be a "co-result". Thus, if the arithmetic result is Vectorised, so
  17 is the CR Field "co-result", which puts both firmly out of scope for
  18 this section.
  19
  20 Other modes are still applicable and include:
  21
  22 * Data-dependent fail-first
  23 * Scalar and parallel reduction
  24 * Predicate-result
  25
  26 Data-dependent Fail-first is useful to truncate VL based on
  27 analysis of a Condition Register result bit.  Reduction is useful
  28 for turning a Vector of Condition Register Fields into one
  29 single Condition Register. Predicate-result is equivalent
  30 to python "filter", in that only elements which pass a test
  31 will end up actually being modified. This is in effect the same
  32 as ANDing the Condition Test with the destination predicate
  33 mask (hence the name, "predicate-result").
  34
  35 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  36
  37 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  38 | - | - | ----- | --- |---------|----------------- |
  39 |dz |VLi| 01    | inv |  CR-bit | Ffirst 3-bit mode      |
  40 |sz |VLi| 01    | inv |  dz Rc1 | Ffirst 5-bit mode       |
  41 | / | / | 00    |   0 |  dz  sz | normal mode                      |
  42 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  43 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
  44 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  45 | / | / | 10    |   / | /   /   |  RESERVED |
  46 |dz | / | 11    | inv | CR-bit  |  3-bit pred-result CR sel |
  47 | / | / | 11    | inv | dz  sz  |  5-bit pred-result z/nonz |
  48
  49 Fields:
  50
  51 TODO
  52
  53 # Data-dependent fail-first on CR operations
  54
  55 Data-dependent SVP64 Vectorised Operations involving the creation or
  56 modification of a CR require an extra two bits, which are not available
  57 in the compact space of the `MODE` Field. With the concept of element
  58 width overrides being meaningless for CR Fields it is possible to use the
  59 `ELWIDTH` field for extra fields.
  60
  61 Condition Register based operations such as `mfcr` and `crand` can thus
  62 be made more flexible.  However the rules that apply in this section
  63 also apply to future CR-based instructions.
  64
  65 There are two primary different types of CR operations:
  66
  67 * Those which have a 3-bit operand field (referring to a CR Field)
  68 * Those which have a 5-bit operand (referring to a bit within the
  69    whole 32-bit CR)
  70
  71 Examining these two as has already been done it is observed that the
  72 difference may be considered to be that the 5-bit variant provides
  73 additional information about which CR Field bit (EQ, GE, LT, SO) is to
  74 be operated on by the instruction.
  75
  76 Thus, logically, we may set the following rule:
  77
  78 * When a 5-bit CR Result field is used in an instruction, the
  79   `inv, VLi and RC1` variant of Data-Dependent Fail-First
  80   must be used. i.e. the bit of the CR field to be tested is
  81   the one that has just been modified by the operation.
  82 * When a 3-bit CR Result field is used the `inv CRbit` variant
  83   must be used in order to select which CR Field bit shall
  84   be tested (EQ, LE, GE, SO)
  85
  86 The reason why the 3-bit CR variant needs the additional CR-bit
  87 field should be obvious from the fact that the 3-bit CR Field
  88 from the base Power ISA v3.0B operation clearly does not contain
  89 and is missing the two CR Field Selector bits. Thus, these two
  90 bits (to select EQ, LE, GE or SO) must be provided in another
  91 way.
  92
  93 Examples of the former type:
  94
  95 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
  96   to be tested against `inv` is the one selected by `BT`
  97 * mcrf. This has only 3-bit (BF, BFA). In order to select the
  98   bit to be tested, the alternative FFirst encoding must be used.
  99
 100 This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
 101 Mode. This is unfortunste but unavoidable due to encoding pressure
 102 on SVP64.
 103
 104 # Predicate-result Condition Register operations
 105
 106 These are again slightly different compared to SVP64 arithmetic
 107 pred-result (described in [[svp64/appendix]]). The reason is that,
 108 again, for arithmetic operations the production of a CR Field when
 109 Rc=1 is a *co-result* accompanying the main arithmetic result, whereas
 110 for CR-based operations the CR Field or CR bit *is* itself the result
 111 of the operation.
 112
 113     for i in range(VL):
 114         # predication test, skip all masked out elements.
 115         # skips when sz=0
 116         if predicate_masked_out(i):
 117              continue
 118         # result is to go into CR. may be a 4-bit CR Field
 119         # (3-bit mode) or just a single bit (5-bit mode)
 120         result = op(...)
 121         # obtain CRbit from BA result operand field,
 122         # if this CR op has 5-bit CR result operands
 123         if 5bit mode:
 124            CRbit = BA[3:4]
 125         # now test CR, similar to branch
 126         if CRnew[CRbit] != inv:
 127             continue # test failed: cancel store
 128         # result optionally stored
 129         update_CR(result)