openpower/sv/cr_ops.mdwn

   1 # Condition Register SVP64 Operations
   2
   3 Links:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
   6 * [[svp64]]
   7
   8 Condition Register Fields are only 4 bits wide: this presents some
   9 interesting conceptual challenges for SVP64, particularly with respect to element
  10 width (which is clearly meaningless for a 4-bit
  11 collation of Conditions, EQ LT GE SO). Likewise, arithmetic saturation
  12 (an important part of Arithmetic SVP64)
  13 has no meaning. Additionally, extra modes are required that only make
  14 sense for Vectorised CR Operations. Consequently an alternative Mode Format is required.
  15
  16 This alternative mapping **only** applies to instructions that **only**
  17 reference a CR Field or CR bit as the sole exclusive result. This section
  18 **does not** apply to instructions which primarily produce arithmetic
  19 results that also, as an aside, produce a corresponding
  20 CR Field (such as when Rc=1).
  21 Instructions that involve Rc=1 are definitively arithmetic in nature,
  22 where the corresponding Condition Register Field can be considered to
  23 be a "co-result". Such CR Field "co-result" arithmeric operations
  24 are firmly out of scope for
  25 this section.
  26
  27 * Examples of v3.0B instructions to which this section does
  28   apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands).
  29 * Examples to which this section does **not** apply include
  30   `fadds.` and `subf.` which both produce arithmetic results
  31   (and a CR Field co-result).
  32
  33 Other modes are still applicable and include:
  34
  35 * **Data-dependent fail-first**.
  36   useful to truncate VL based on
  37   analysis of a Condition Register result bit.
  38 * **Scalar and parallel reduction**.
  39   Reduction is useful
  40 for turning a Vector of Condition Register Fields into one
  41 single Condition Register.
  42 * **Predicate-result**.
  43   Equivalent
  44 to python "filter", in that only elements which pass a test
  45 will end up actually being modified. This is in effect the same
  46 as ANDing the Condition Test with the destination predicate
  47 mask (hence the name, "predicate-result").
  48
  49 Predicate-result is a particularly powerful strategic mode
  50 in that it is the interaction of a source predicate, destination predicate,
  51 input operands *and* the output result, all combining to influence
  52 what actually goes into the Condition Register File. Given that
  53 predicates may themselves be Condition Registers it can be seen that
  54 there could potentially be up to **six** CR Fields involved in
  55 the execution of Predicate-result Mode.
  56
  57 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  58
  59 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  60 | - | - | ----- | --- |---------|----------------- |
  61 | / | / | 00    |   0 |  dz  sz | normal mode                      |
  62 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  63 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
  64 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  65 |dz |VLi| 01    | inv |  CR-bit | Ffirst 3-bit mode      |
  66 |sz |VLi| 01    | inv |  dz Rc1 | Ffirst 5-bit mode       |
  67 | / | / | 10    |   / | /   /   |  RESERVED |
  68 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |
  69 | / |SNZ| 11    | inv | dz  sz  |  5-bit pred-result z/nonz |
  70
  71 Fields:
  72
  73 TODO
  74
  75 # Data-dependent fail-first on CR operations
  76
  77 The principle of data-dependent fail-first is that if a Condition Test
  78 fails then VL (Vector Length) is truncated at that point. In the case
  79 of Arithmetic SVP64 Operations the Condition Register Field generated from
  80 Rc=1 is used, however with CR-based operations that CR result is provided
  81 by the operation itself.
  82
  83 Data-dependent SVP64 Vectorised Operations involving the creation or
  84 modification of a CR can require an extra two bits, which are not available
  85 in the compact space of the SVP64 RM `MODE` Field. With the concept of element
  86 width overrides being meaningless for CR Fields it is possible to use the
  87 `ELWIDTH` field for alternative purposes.
  88
  89 Condition Register based operations such as `sv.mfcr` and `sv.crand` can thus
  90 be made more flexible.  However the rules that apply in this section
  91 also apply to future CR-based instructions.
  92
  93 There are two primary different types of CR operations:
  94
  95 * Those which have a 3-bit operand field (referring to a CR Field)
  96 * Those which have a 5-bit operand (referring to a bit within the
  97    whole 32-bit CR)
  98
  99 Examining these two types it is observed that the
 100 difference may be considered to be that the 5-bit variant provides
 101 additional information about which CR Field bit (EQ, GE, LT, SO) is to
 102 be operated on by the instruction.
 103 Thus, logically, we may set the following rule:
 104
 105 * When a 5-bit CR Result field is used in an instruction, the
 106   5-bit variant of Data-Dependent Fail-First
 107   must be used. i.e. the bit of the CR field to be tested is
 108   the one that has just been modified (created) by the operation.
 109 * When a 3-bit CR Result field is used the 3-bit variant
 110   must be used, providing as it does the missing `CRbit`
 111   in order to select which CR Field bit of the result shall
 112   be tested (EQ, LE, GE, SO)
 113
 114 The reason why the 3-bit CR variant needs the additional CR-bit
 115 field should be obvious from the fact that the 3-bit CR Field
 116 from the base Power ISA v3.0B operation clearly does not contain
 117 and is missing the two CR Field Selector bits. Thus, these two
 118 bits (to select EQ, LE, GE or SO) must be provided in another
 119 way.
 120
 121 Examples of the former type:
 122
 123 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
 124   to be tested against `inv` is the one selected by `BT`
 125 * mcrf. This has only 3-bit (BF, BFA). In order to select the
 126   bit to be tested, the alternative encoding must be used.
 127   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
 128   of BF to be tested is identified.
 129
 130 # Predicate-result Condition Register operations
 131
 132 These are again slightly different compared to SVP64 arithmetic
 133 pred-result (described in [[svp64/appendix]]). The reason is that,
 134 again, for arithmetic operations the production of a CR Field when
 135 Rc=1 is a *co-result* accompanying the main arithmetic result, whereas
 136 for CR-based operations the CR Field (referred to by a 3-bit
 137 v3.0B base operand from e.g. `mfcr`) or CR bit (referred to by a 5-bit operand from e.g. `crnor`)
 138 *is* itself the explicit and sole result of the operation.
 139
 140 Therefore, logically, Predicate-result needs to be adapted to
 141 test the actual result of the CR-based instruction, rather than
 142 test the co-resultant CR when Rc=1.
 143
 144     for i in range(VL):
 145         # predication test, skip all masked out elements.
 146         # skips when sz=0
 147         if sz=0 and predicate_masked_out(i):
 148              continue
 149         if predicate_masked_out(i):
 150            if 5bit mode:
 151               # only one bit of CR to update
 152               result = SNZ
 153            else
 154               # four copies of SNZ
 155               result = SNZ || SNZ || SNZ || SNZ
 156         else
 157            # result is to go into CR. may be a 4-bit CR Field
 158            # (3-bit mode) or just a single bit (5-bit mode)
 159            result = op(...)
 160         if 5bit mode:
 161            # if this CR op has 5-bit CR result operands
 162            # the single bit result is what must be tested
 163            to_test = result
 164         else
 165            # if however this is a 3-bit CR *field* result
 166            # then the bit to be tested must be selected
 167            to_test = result[CRbit]
 168         # now test CR, similar to branch
 169         if to_test != inv:
 170             continue # test failed: cancel store
 171         # result optionally stored
 172         update_CR(result)