openpower/sv/discussion.mdwn

   1 # UTF-8 SV
   2
   3 http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/001000.html
   4
   5 turns out that is a somewhat different link than the one I thought I
   6 linked to, the one I intended to link to covers full vectorized
   7 validation including non-ASCII UTF-8, rather than just vectorizing a
   8 check-for-ASCII.
   9
  10 I think this is it:
  11 https://arxiv.org/pdf/2010.03090.pdf
  12
  13 # Book start
  14
  15 Chapter 8. Simple-V Facility
  16 Section 8.1 Introduction: The Simple-V facility (abbreviated as SV) provides a way for a programmer to specify that an instruction, or a sequence of instructions, are to be repeatedly executed using successive register operands. It also provides controls to enable individual iterations to be skipped, to address larger sets of general and floating-point registers, to process registers as arrays of smaller elements, and to specify that arithmetic operations should generate saturated values in case of overflow. ...etc... {Describe the facility and what you can do with it at a mid to high level; don't include rationale for design decisions or warnings about possible alternative designs. Don't waste space inveighing against SIMD, etc.}
  17
  18 Section 8.2 Simple-V Facility Registers
  19 8.2.1 Expanded GPR register set
  20 8.2.2 Expanded FPR register set
  21 8.3.3 Expanded CR register set
  22 8.3.4 Simple-V SPRs (SVSTATE, SVLR) {Description of SVSRR0 etc. would go in new sections in Book III}
  23
  24 Section 8.3 Simple-V Instruction Encoding
  25 8.3.1 Introduction {Describe use of prefix instruction word, which instructions can be vectorized, etc}
  26 8.3.2 Simple-V prefix encoding details
  27
  28 Section 8.4 Simple-V Execution Model
  29
  30 Section 8.5 Simple-V Instruction Descriptions {setvl etc.}
  31
  32 # questions
  33
  34 There is much confusion about what the little-endian mapping of the register file means and how it is carried out. Do the registers effectively get byte-swapped by bits? by bytes? by elements? Isn't the LE mapping going to be extremely awkward in a system running in big-endian mode?
  35 Similarly, addressing the CR file by bit with little-endian numbering seems like it will create awkwardness.
  36 Does "truncate" mean the same as "terminate" here?
  37 Emulating 64-bit processors on a 32-bit CPU is not an objective. Perhaps your comments on the existing Power ISA could be toned down a bit?
  38 Phrases like "Cray-style vectors" and "DSP-style zero-overhead looping" are not particularly informative or well-defined, since many people in your audience will not be familiar either with Cray computer architecture or with DSPs.
  39 The process of taking interrupts, what state is saved and how, and then restored so execution can continue, all need to be spelled out in more detail. Can an asynchronous interrupt (e.g. external interrupt) occur in the middle of a vectorized instruction? How does that work?
  40 There seems to be no provision for saving SVSTATE when an event-based branch (Book II chapter 6) occurs. Should there be?
  41 How do vectorized conditional branches work and how is SVLR used?
  42 How do vectorized floating-point instructions set FPSCR, given that it isn't vectorized?