openpower/sv/executive_summary.mdwn

   1 Simple-V is a Scalable Vector ISA Extension specifically tailored
   2 for the uniquely powerful capabilities of the Power ISA.
   3
   4 **Simple-V does not modify harm or corrupt the existing Power ISA** and
   5 does not interfere with an existing system.  It needs only a small
   6 allocation of opcodes (five) to implement, whereas any other Vector
   7 implementation would require an intrusive fundamental overhaul of the
   8 Power ISA.
   9
  10 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
  11 instructions vertical and registers horizontal otherwise it will be
  12 difficult to grasp and appreciate its RISC simplicity.
  13
  14 Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
  15 ubiquitous, the ISA uniform.
  16
  17 * GPUs may implement massive-wide SIMD back-ends, focussing on
  18   number-crunching.
  19 * Existing Multi-issue Superscalar implementations may
  20   insert Simple-V between decode and issue with minimal disruption.
  21 * Single-issue in-order implementations are very straightforward.
  22
  23 All implementations regardless of back-end capability may execute the exact
  24 same binaries *(this is known to be extremely important to the Power ISA
  25 ecosystem)*.
  26
  27 Simple-V is **not RISC-V and is not RISC-V Vectors**. NEC SX Aurora,
  28 RVV and Simple-V are all based on Cray-style Vectors hence the similarity,
  29 the provision of a `setvl` instruction and why they are each called
  30 "Scalable" Vectors because it is the `setvl` instruction that
  31 presents the programmer with explicit control over Vector length.
  32
  33 ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
  34 **do not provide Scalability to the Programmer** (SVE2 is **Silicon**
  35 Scalable, not **Programmer** Scalable: the distinction is profoundly
  36 important).
  37 For Predicated SIMD, Programmers must emulate scaling
  38 through explicit predicate masking, which increases instruction count in
  39 hot-loops.
  40
  41 We invented Simple-V to be simple because we don't like complicated.
  42
  43 Links to Simulator, installation scripts, and Unit tests:
  44
  45 * **Unit tests and simulator for Power ISA v3.0 and SVP64**
  46   <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD>
  47 * **pypowersim tutorial** <https://libre-soc.org/docs/pypowersim/>
  48 * **several thousand more ISA unit tests**
  49   <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>
  50 * **demo, showing 4.5x reduction in program size for MP3 decode, greatly
  51   simplifies assembler development**
  52   <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>
  53 * **binutils support for SVP64**
  54   <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>
  55 * **Documentation** <https://libre-soc.org/docs>
  56 * **Installation scripts** <https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD>