openpower/sv/executive_summary.mdwn

   1 **Simple-V** is a Scalable Vector ISA Extension **specifically tailored**
   2 for the uniquely powerful capabilities of the Power ISA. **SVP64**
   3 is the instruction set format.
   4 We invented Simple-V to be simple because we don't like complicated.
   5
   6 **Simple-V does not modify harm or corrupt the existing Power ISA** and
   7 does not interfere with an existing system.  It needs only a small
   8 allocation of opcodes (five) to implement, whereas any other Vector
   9 implementation would require an intrusive fundamental overhaul of the
  10 Power ISA.
  11
  12 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
  13 instructions vertical and registers horizontal otherwise it will be
  14 difficult to grasp and appreciate its RISC simplicity.
  15 Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
  16 ubiquitous, the ISA uniform. The Compliancy Levels offer a means
  17 to scale up in complexity to meet the target application requirements.
  18
  19 * GPUs may implement massive-wide SIMD back-ends, focussing on
  20   number-crunching.
  21 * Existing Multi-issue Superscalar implementations may
  22   insert Simple-V between decode and issue with minimal disruption.
  23 * Single-issue in-order implementations are very straightforward.
  24 * Inter-core communication (OpenCAPI, other) may still be utilised
  25   because SVP64 fundamentally remains and respects the Power ISA.
  26
  27 All implementations regardless of back-end capability may execute the exact
  28 same binaries *(this is known to be extremely important to the Power ISA
  29 ecosystem)*.
  30 *If not done as carefully as SVP64, the addition of any other Scalable
  31 Vector Extension would require a significant number of opcodes, putting
  32 further pressure on Major Opcode space which was never designed with
  33 Scalable Vectors in mind.  Contrast with RISC-V which was
  34 designed over a 7 year period with Cray-style Vectors right from the start.*
  35
  36 Even with this amount of time spent, SVP64 exceeds the capability of RVV.
  37 RISC-V could have been significantly enhanced if Simple V had been applied
  38 to it: this possibility was investigated very early but the decision was
  39 made to go with Power ISA instead.
  40
  41 Therefore it is crucial to note that
  42 Simple-V is **not RISC-V and is not RISC-V Vectors**.
  43 [NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
  44 [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc),
  45 [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
  46 [MRISC32](https://github.com/mrisc32/mrisc32)
  47 are all based on
  48 [Cray-style Scalable Vectors](https://en.m.wikipedia.org/wiki/Cray-1)
  49 of 50 years ago, hence the similarity,
  50 the provision of a `setvl` instruction, and why they are each called
  51 "Scalable" Vectors, because it is the `setvl` instruction that
  52 presents the **programmer** with explicit control over Vector length.
  53
  54 VSX and NEON are PackedSIMD, and
  55 AVX-512 and ARM SVE2 are Predicated SIMD ISAs.
  56 **None of them provide Scalability to the Programmer**.  SVE2 is **Silicon**
  57 Scalable, not **Programmer** Scalable: the distinction is profoundly
  58 important (already
  59 [causing problems](https://bugs.libre-soc.org/show_bug.cgi?id=893#c15) ).
  60 For Predicated SIMD, Programmers must emulate Cray-style scaling
  61 through explicit predicate masking, which increases instruction count in
  62 hot-loops.
  63
  64
  65 | description, URL                                                                            |
  66 |---------------------------------------------------------------------------------------------|
  67 | **Unit tests and simulator for Power ISA v3.0 and SVP64**                                   |
  68 | <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD> |
  69 | **pypowersim tutorial**                                                                     |
  70 | <https://libre-soc.org/docs/pypowersim/>                                                    |
  71 | **several thousand more ISA unit tests**                                                    |
  72 |  <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>       |
  73 | **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** |
  74 | <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>           |
  75 | **binutils support for DRAFT SVP64 (now upstream)**                                                              |
  76 | <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>            |