openpower/sv/executive_summary.mdwn

   1 Simple-V is a Scalable Vector ISA Extension specifically tailored
   2 for the uniquely powerful capabilities of the Power ISA.
   3
   4 **Simple-V does not modify harm or corrupt the existing Power ISA** and
   5 does not interfere with an existing system.  It needs only a small
   6 allocation of opcodes (five) to implement, whereas any other Vector
   7 implementation would require an intrusive fundamental overhaul of the
   8 Power ISA.
   9
  10 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
  11 instructions vertical and registers horizontal otherwise it will be
  12 difficult to grasp and appreciate its RISC simplicity.
  13
  14 Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
  15 ubiquitous, the ISA uniform.
  16
  17 * GPUs may implement massive-wide SIMD back-ends, focussing on
  18   number-crunching.
  19 * Existing Multi-issue Superscalar implementations may
  20   insert Simple-V between decode and issue with minimal disruption.
  21 * Single-issue in-order implementations are very straightforward.
  22 * Inter-core communication (OpenCAPI, other) may still be utilised
  23   because SVP64 fundamentally remains and respects the Power ISA.
  24
  25 All implementations regardless of back-end capability may execute the exact
  26 same binaries *(this is known to be extremely important to the Power ISA
  27 ecosystem)*.
  28
  29 *If not done as carefully as SVP64, the addition of any other Scalable
  30 Vector Extension would require a significant number of opcodes, putting
  31 further pressure on Major Opcode space which was never designed with
  32 Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
  33 designed over a 7 year period with Cray-style Vectors right from the start.*
  34
  35 Simple-V is **not RISC-V and is not RISC-V Vectors**.
  36 [NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
  37 [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc), [Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
  38 [MRISC32](https://github.com/mrisc32/mrisc32)
  39 are all based on Cray-style Scalable Vectors
  40 of 30 years ago, hence the similarity,
  41 the provision of a `setvl` instruction, and why they are each called
  42 "Scalable" Vectors, because it is the `setvl` instruction that
  43 presents the **programmer** with explicit control over Vector length.
  44
  45 ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
  46 **do not provide Scalability to the Programmer**.  SVE2 is **Silicon**
  47 Scalable, not **Programmer** Scalable: the distinction is profoundly
  48 important.
  49 For Predicated SIMD, Programmers must emulate Cray-style scaling
  50 through explicit predicate masking, which increases instruction count in
  51 hot-loops.
  52
  53 We invented Simple-V to be simple because we don't like complicated.
  54
  55 | description, URL                                                                            |
  56 |---------------------------------------------------------------------------------------------|
  57 | **Unit tests and simulator for Power ISA v3.0 and SVP64**                                   |
  58 | <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD> |
  59 | - - -                                                                                       |
  60 | **pypowersim tutorial**                                                                     |
  61 | <https://libre-soc.org/docs/pypowersim/>                                                    |
  62 | - - -                                                                                       |
  63 | **several thousand more ISA unit tests**                                                    |
  64 |  <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>       |
  65 | - - -                                                                                       |
  66 | **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** |
  67 | <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>           |
  68 | - - -                                                                                       |
  69 | **binutils support for SVP64**                                                              |
  70 | <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>            |