openpower/sv/fclass.mdwn

   1 # fclass
   2
   3 In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision.  Thus when elwidth=FP32 fptstsp will test half that precision, at FP16.
   4
   5 based on xvtstdcsp v3.0B p768 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign.
   6
   7 unlike xvtstdcsp the result is stored in a Condition Register specified by BF.
   8 this allows it to be used as a predicate mask.  setb may be used to create the equivalent of xvtstdcsp if desired.
   9
  10 | 0.5| 6..10 |11.15| 16.20 | 21...30 |31|  name   |
  11 | -- | ----- | --- | ----- | ------- |--| ------- |
  12 | PO | BF/dx | FRA | dc    | XO      |dm| fptstsp |
  13
  14 ```
  15 DCMX <- dc || dm || dx
  16 src  <- (FRA)[32:63]
  17 sign  <- src[0]
  18 exponent  <- src[1:8]
  19 fraction  <- src[9:31]
  20 class.Infinity  <- (exponent = 0xFF) & (fraction = 0)
  21 class.NaN  <- (exponent = 0xFF) & (fraction != 0)
  22 class.Zero  <- (exponent = 0x00) & (fraction = 0)
  23 class.Denormal  <- (exponent = 0x00) & (fraction != 0)
  24 CR{BF} <- ((DCMX[0] & class.NaN & !sign)  |
  25            (DCMX[1] & class.NaN & sign))  ||
  26           ((DCMX[6] & class.Denormal & !sign) |
  27            (DCMX[7] & class.Denormal & sign)) ||
  28           ((DCMX[2] & class.Infinity & !sign) |
  29            (DCMX[3] & class.Infinity & sign)) ||
  30           ((DCMX[4] & class.Zero & !sign) |
  31            (DCMX[5] & class.Zero & sign))
  32 ```
  33
  34 64 bit variant fptstdp is as follows:
  35
  36 ```
  37 sign <- src.bit[0]
  38 exponent <- src.bit[1:11]
  39 fraction <- src.bit[12:63]
  40       exponent & 7FF
  41 ```