3 based on xvtstdcsp v3.0B p760 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign. When VSX is not implemented these instructions become necessary.
5 unlike xvtstdcsp the result is stored in a Condition Register
7 this allows it to be used as a predicate mask. setb may be used to create the equivalent of xvtstdcsp if desired.
9 The CR Field bits are set in a reasonably logical fashion:
11 * BF.EQ is set if FRB is zero
12 * BF.LE is set if FRB is non-normalises
13 * BF.GE is set if FRB is infinite
14 * BF.SO is set if FRB is NaN
16 | 0.5| 6.8 |9..15 | 16.20 | 21...30 |31| name | Form |
17 | -- | --- | -- | ----- | ------- |--| ------- | ------ |
18 | PO | BF | DCMX | FRB | XO |dm2| fptstsp | X-Form|
26 class.Infinity <- (exponent = 0xFF) & (fraction = 0)
27 class.NaN <- (exponent = 0xFF) & (fraction != 0)
28 class.Zero <- (exponent = 0x00) & (fraction = 0)
29 class.Denormal <- (exponent = 0x00) & (fraction != 0)
30 CR{BF} <- ((dcmx[0] & class.NaN & !sign) |
31 (dcmx[1] & class.NaN & sign)) ||
32 ((dcmx[2] & class.Infinity & !sign) |
33 (dcmx[3] & class.Infinity & sign)) ||
34 ((dcmx[6] & class.Denormal & !sign) |
35 (dcmx[7] & class.Denormal & sign)) ||
36 ((dcmx[4] & class.Zero & !sign) |
37 (dcmx[5] & class.Zero & sign))
40 64 bit variant fptstdp is as follows:
46 fraction <- src[12:63]
50 In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision. Thus when elwidth=FP32 fptstsp will test half that precision, at FP16.