openpower/sv/fclass.mdwn

   1 # fclass
   2
   3 In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision.  Thus when elwidth=FP32 fptstsp will test half that precision, at FP16.
   4
   5 based on xvtstdcsp v3.0B p768 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign.  unlike xvtstdcsp the result is stored in a Condition Register specified by BF.
   6
   7 | 0.5| 6..10 |11.15| 16.20 | 21...30 |31|  name   |
   8 | -- | ----- | --- | ----- | ------- |--| ------- |
   9 | PO | BF/dx | FRA | dc    | XO      |dm| fptstsp |
  10
  11 ```
  12 DCMX <- dc || dm || dx
  13 src  <- (FRA)[32:63]
  14 sign  <- src[0]
  15 exponent  <- src[1:8]
  16 fraction  <- src[9:31]
  17 class.Infinity  <- (exponent = 0xFF) & (fraction = 0)
  18 class.NaN  <- (exponent = 0xFF) & (fraction != 0)
  19 class.Zero  <- (exponent = 0x00) & (fraction = 0)
  20 class.Denormal  <- (exponent = 0x00) & (fraction != 0)
  21 CR{BF} <- ((DCMX[0] & class.NaN & !sign)  |
  22            (DCMX[1] & class.NaN & sign))  ||
  23           ((DCMX[6] & class.Denormal & !sign) |
  24            (DCMX[7] & class.Denormal & sign)) ||
  25           ((DCMX[2] & class.Infinity & !sign) |
  26            (DCMX[3] & class.Infinity & sign)) ||
  27           ((DCMX[4] & class.Zero & !sign) |
  28            (DCMX[5] & class.Zero & sign))
  29 ```
  30
  31 64 bit variant fptstdp is as follows:
  32
  33 ```
  34 sign <- src.bit[0]
  35 exponent <- src.bit[1:11]
  36 fraction <- src.bit[12:63]
  37       exponent & 7FF
  38 ```