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[libreriscv.git] / openpower / sv / implementation.mdwn
1 # Implementation
2
3 This page covers and coordinates implementing SV. The basic concept is
4 to go step-by-step through the [[sv/overview]] adding each feature,
5 one at a time.
6
7 Links:
8
9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
11 assembler translator
12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
13 assembler translator
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
16
17 # Code to convert
18
19 There are three projects:
20
21 * TestIssuer (the HDL)
22 * ISACaller (the python-based simulator)
23 * power-gem5 (a cycle accurate simulator)
24
25 Each of these needs to have SV augmentation, and the best way to
26 do it is if they are all done at the same time, implementing the same
27 incremental feature.
28
29 # Critical tasks
30
31 These are prerequisite tasks:
32
33 * power-gem5 automanagement, similar to pygdbmi for starting qemu
34 - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
35 just use pygdbmi
36 - needs remote gdb first https://github.com/gem5/gem5/blob/stable/src/arch/riscv/remote_gdb.cc
37 * c++, c and python macros for generating [[sv/svp64]] assembler
38 (svp64 prefixes)
39 - python svp64 underway, minimalist sufficient for FU unit tests
40 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
41
42 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
43
44 * Lauri:
45 * Jacob: C/C++ header for using SV through inline assembly
46 * Cesar: TestIssuer FSM
47 * Alain: power-gem5
48 * Cole:
49 * Luke: ISACaller, python-assembler-generator-class
50 * Tobias:
51 * Alexandre: binutils-svp64-assembler
52