openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22
  23 # Code to convert
  24
  25 There are four projects:
  26
  27 * TestIssuer (the HDL)
  28 * ISACaller (the python-based simulator)
  29 * power-gem5 (a cycle accurate simulator)
  30 * Microwatt (VHDL)
  31
  32 Each of these needs to have SV augmentation, and the best way to
  33 do it is if they are all done at the same time, implementing the same
  34 incremental feature.
  35
  36 # Critical tasks
  37
  38 These are prerequisite tasks:
  39
  40 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  41   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  42   just use pygdbmi
  43   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  44 * c++, c and python macros for generating [[sv/svp64]] assembler
  45   (svp64 prefixes)
  46   - python svp64 underway, minimalist sufficient for FU unit tests
  47 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  48 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  49   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  50   - INT and CR EXTRA svp64 fields completed.
  51
  52 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  53
  54 * Lauri:
  55 * Jacob: C/C++ header for using SV through inline assembly
  56 * Cesar: TestIssuer FSM
  57 * Alain: power-gem5
  58 * Cole:
  59 * Luke: ISACaller, python-assembler-generator-class
  60 * Tobias:
  61 * Alexandre: binutils-svp64-assembler
  62 * Paul: microwatt
  63
  64 # Adding SV
  65
  66 order: listed in [[sv/overview]]
  67
  68 ## svp64 decoder
  69
  70 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  71
  72 * ISACaller: TODO
  73 * power-gem5: TODO
  74 * TestIssuer: TODO
  75 * Microwatt: TODO
  76 * python-based assembler-translator: 40% done (lkcl)
  77 * c++ macros: underway (jacob)
  78
  79 Links:
  80
  81 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  82 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  83
  84 ## SVSTATE SPR needed
  85
  86 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  87
  88 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
  89
  90     num name    priv  width
  91     704,SVSTATE,no,no,32
  92     720,SVSRR0,yes,yes,32
  93
  94 Progress:
  95
  96 * ISACaller: TODO
  97 * power-gem5: TODO
  98 * TestIssuer: TODO
  99 * Microwatt: TODO
 100
 101 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 102
 103 ## sv.setvl
 104
 105 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 106
 107 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 108 * ISACaller: TODO
 109 * power-gem5: TODO
 110 * TestIssuer: TODO
 111 * Microwatt: TODO
 112
 113 ## SVSRR0 for exceptions
 114
 115 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 116
 117 * ISACaller: TODO
 118 * power-gem5: TODO
 119 * TestIssuer: TODO
 120 * Microwatt: TODO
 121
 122 ## VL for-loop
 123
 124 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 125
 126 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 127
 128 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 129
 130 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 131
 132 * ISACaller: TODO
 133 * power-gem5: TODO
 134 * TestIssuer: TODO
 135 * Microwatt: TODO
 136
 137 ## Increasing register file sizes
 138
 139 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 140
 141 ## Single Predication
 142
 143 TODO
 144
 145 ## Element width overrides
 146
 147 TODO