3 This page covers and coordinates implementing SV. The basic concept is
4 to go step-by-step through the [[sv/overview]] adding each feature,
9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
21 (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
25 There are four projects:
27 * TestIssuer (the HDL)
28 * ISACaller (the python-based simulator)
29 * power-gem5 (a cycle accurate simulator)
32 Each of these needs to have SV augmentation, and the best way to
33 do it is if they are all done at the same time, implementing the same
38 These are prerequisite tasks:
40 * power-gem5 automanagement, similar to pygdbmi for starting qemu
41 - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
43 - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
44 * c++, c and python macros for generating [[sv/svp64]] assembler
46 - python svp64 underway, minimalist sufficient for FU unit tests
47 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
48 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
50 - INT and CR EXTRA svp64 fields completed.
51 * SVP64PowerDecoder2, used to identify SVP64 Prefixes. DONE.
53 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
56 * Jacob: C/C++ header for using SV through inline assembly
57 * Cesar: TestIssuer FSM
60 * Luke: ISACaller, python-assembler-generator-class
62 * Alexandre: binutils-svp64-assembler
67 order: listed in [[sv/overview]]
71 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome. sv_analyse.py creates the CSV files, SVP64RM class picks them up.
73 * ISACaller: part done. svp64 detected, PowerDecoder2 in use
75 * TestIssuer: part done. svp64 detected, PowerDecoder2 in use.
77 * python-based assembler-translator: 40% done (lkcl)
78 * c++ macros: underway (jacob)
82 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
83 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
87 This is a peer of MSR but is stored in an SPR. It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
89 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
102 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
106 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR. the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
108 * LibreSOC OpenPOWER wiki fields/forms: DONE. pseudocode: TODO
114 ## SVSRR0 for exceptions
116 SV's SVSTATE context is effectively a Sub-PC. On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same. SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1. This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
125 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1. Register numbers are incremented by one if marked as vector.
127 *This loop goes in between decode and issue phases*. It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*. Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
129 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
131 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
133 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
135 * TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
138 Remember the following register files need to have for-loops, plus
142 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
143 * Condition Registers. see note below
146 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1. Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments. The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
148 ## Increasing register file sizes
150 TODO. INTs, FPs, CRs, these all increase to 128. Welcome To Vector ISAs.
152 ## Single Predication
156 ## Element width overrides