openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  16   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  17
  18
  19 # Code to convert
  20
  21 There are three projects:
  22
  23 * TestIssuer (the HDL)
  24 * ISACaller (the python-based simulator)
  25 * power-gem5 (a cycle accurate simulator)
  26
  27 Each of these needs to have SV augmentation, and the best way to
  28 do it is if they are all done at the same time, implementing the same
  29 incremental feature.
  30
  31 # Critical tasks
  32
  33 These are prerequisite tasks:
  34
  35 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  36   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  37   just use pygdbmi
  38   - needs remote gdb first https://github.com/gem5/gem5/blob/stable/src/arch/riscv/remote_gdb.cc
  39 * c++, c and python macros for generating [[sv/svp64]] assembler
  40   (svp64 prefixes)
  41   - python svp64 underway, minimalist sufficient for FU unit tests
  42 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  43
  44 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  45
  46 * Lauri:
  47 * Jacob: C/C++ header for using SV through inline assembly
  48 * Cesar: TestIssuer FSM
  49 * Alain: power-gem5
  50 * Cole:
  51 * Luke: ISACaller, python-assembler-generator-class
  52 * Tobias:
  53 * Alexandre: binutils-svp64-assembler
  54
  55 # Adding SV
  56
  57 order: listed in [[sv/overview]]
  58
  59 ## sv.setvl
  60
  61 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.
  62
  63 * ISACaller: TODO
  64 * power-gem5: TODO
  65 * TestIssuer: TODO
  66
  67 ## VL for-loop
  68
  69 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1
  70
  71 * ISACaller: TODO
  72 * power-gem5: TODO
  73 * TestIssuer: TODO