openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19
  20
  21 # Code to convert
  22
  23 There are four projects:
  24
  25 * TestIssuer (the HDL)
  26 * ISACaller (the python-based simulator)
  27 * power-gem5 (a cycle accurate simulator)
  28 * Microwatt
  29
  30 Each of these needs to have SV augmentation, and the best way to
  31 do it is if they are all done at the same time, implementing the same
  32 incremental feature.
  33
  34 # Critical tasks
  35
  36 These are prerequisite tasks:
  37
  38 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  39   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  40   just use pygdbmi
  41   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  42 * c++, c and python macros for generating [[sv/svp64]] assembler
  43   (svp64 prefixes)
  44   - python svp64 underway, minimalist sufficient for FU unit tests
  45 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  46
  47 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  48
  49 * Lauri:
  50 * Jacob: C/C++ header for using SV through inline assembly
  51 * Cesar: TestIssuer FSM
  52 * Alain: power-gem5
  53 * Cole:
  54 * Luke: ISACaller, python-assembler-generator-class
  55 * Tobias:
  56 * Alexandre: binutils-svp64-assembler
  57 * Paul: microwatt
  58
  59 # Adding SV
  60
  61 order: listed in [[sv/overview]]
  62
  63 ## svp64 decoder
  64
  65 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  66
  67 * ISACaller: TODO
  68 * power-gem5: TODO
  69 * TestIssuer: TODO
  70 * Microwatt: TODO
  71 * python-based assembler-translator: 40% done (lkcl)
  72 * c++ macros: underway (jacob)
  73
  74 Links:
  75
  76 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  77 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  78
  79 ## SVSTATE SPR needed
  80
  81 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  82
  83 * ISACaller: TODO
  84 * power-gem5: TODO
  85 * TestIssuer: TODO
  86 * Microwatt: TODO
  87
  88 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
  89
  90 ## sv.setvl
  91
  92 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
  93
  94 * ISACaller: TODO
  95 * power-gem5: TODO
  96 * TestIssuer: TODO
  97 * Microwatt: TODO
  98
  99 ## SVSRR0 for exceptions
 100
 101 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 102
 103 * ISACaller: TODO
 104 * power-gem5: TODO
 105 * TestIssuer: TODO
 106 * Microwatt: TODO
 107
 108 ## VL for-loop
 109
 110 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 111
 112 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected.
 113
 114 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 115
 116 * ISACaller: TODO
 117 * power-gem5: TODO
 118 * TestIssuer: TODO
 119 * Microwatt: TODO