openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  20  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  21
  22
  23 # Code to convert
  24
  25 There are four projects:
  26
  27 * TestIssuer (the HDL)
  28 * ISACaller (the python-based simulator)
  29 * power-gem5 (a cycle accurate simulator)
  30 * Microwatt (VHDL)
  31
  32 Each of these needs to have SV augmentation, and the best way to
  33 do it is if they are all done at the same time, implementing the same
  34 incremental feature.
  35
  36 # Critical tasks
  37
  38 These are prerequisite tasks:
  39
  40 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  41   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  42   just use pygdbmi
  43   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  44 * c++, c and python macros for generating [[sv/svp64]] assembler
  45   (svp64 prefixes)
  46   - python svp64 underway, minimalist sufficient for FU unit tests
  47 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  48
  49 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  50
  51 * Lauri:
  52 * Jacob: C/C++ header for using SV through inline assembly
  53 * Cesar: TestIssuer FSM
  54 * Alain: power-gem5
  55 * Cole:
  56 * Luke: ISACaller, python-assembler-generator-class
  57 * Tobias:
  58 * Alexandre: binutils-svp64-assembler
  59 * Paul: microwatt
  60
  61 # Adding SV
  62
  63 order: listed in [[sv/overview]]
  64
  65 ## svp64 decoder
  66
  67 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  68
  69 * ISACaller: TODO
  70 * power-gem5: TODO
  71 * TestIssuer: TODO
  72 * Microwatt: TODO
  73 * python-based assembler-translator: 40% done (lkcl)
  74 * c++ macros: underway (jacob)
  75
  76 Links:
  77
  78 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  79 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  80
  81 ## SVSTATE SPR needed
  82
  83 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  84
  85 * ISACaller: TODO
  86 * power-gem5: TODO
  87 * TestIssuer: TODO
  88 * Microwatt: TODO
  89
  90 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
  91
  92 ## sv.setvl
  93
  94 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
  95
  96 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
  97 * ISACaller: TODO
  98 * power-gem5: TODO
  99 * TestIssuer: TODO
 100 * Microwatt: TODO
 101
 102 ## SVSRR0 for exceptions
 103
 104 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 105
 106 * ISACaller: TODO
 107 * power-gem5: TODO
 108 * TestIssuer: TODO
 109 * Microwatt: TODO
 110
 111 ## VL for-loop
 112
 113 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 114
 115 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 116
 117 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 118
 119 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 120
 121 * ISACaller: TODO
 122 * power-gem5: TODO
 123 * TestIssuer: TODO
 124 * Microwatt: TODO