3 This page covers and coordinates implementing SV. The basic concept is
4 to go step-by-step through the [[sv/overview]] adding each feature,
9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
22 There are four projects:
24 * TestIssuer (the HDL)
25 * ISACaller (the python-based simulator)
26 * power-gem5 (a cycle accurate simulator)
29 Each of these needs to have SV augmentation, and the best way to
30 do it is if they are all done at the same time, implementing the same
35 These are prerequisite tasks:
37 * power-gem5 automanagement, similar to pygdbmi for starting qemu
38 - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
40 - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
41 * c++, c and python macros for generating [[sv/svp64]] assembler
43 - python svp64 underway, minimalist sufficient for FU unit tests
44 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
46 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
49 * Jacob: C/C++ header for using SV through inline assembly
50 * Cesar: TestIssuer FSM
53 * Luke: ISACaller, python-assembler-generator-class
55 * Alexandre: binutils-svp64-assembler
60 order: listed in [[sv/overview]]
64 An autogenerator containing CSV files is available so that the task of creating deciders is not burdensome. sv_analyse.py creates the CSV files, SVP64RM class picks them up.
70 * python-based assembler-translator: 40% done (lkcl)
71 * c++ macros: underway (jacob)
75 This is a peer of MSR but is stored in an SPR. It should be considered part of the state of PC+MSR.
84 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR. the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
91 ## SVSRR0 for exceptions
93 SV's SVSTATE context is effectively a Sub-PC. On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same. SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1. This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
102 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1