openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
  23 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
  24
  25 # Code to convert
  26
  27 There are five projects:
  28
  29 * TestIssuer (the HDL)
  30 * ISACaller (the python-based simulator)
  31 * power-gem5 (a cycle accurate simulator)
  32 * Microwatt (VHDL)
  33 * gcc and binutils
  34
  35 Each of these needs to have SV augmentation, and the best way to
  36 do it is if they are all done at the same time, implementing the same
  37 incremental feature.
  38
  39 # Critical tasks
  40
  41 These are prerequisite tasks:
  42
  43 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  44   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  45   just use pygdbmi
  46   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  47 * c++, c and python macros for generating [[sv/svp64]] assembler
  48   (svp64 prefixes)
  49   - python svp64 underway, minimalist sufficient for FU unit tests
  50 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  51 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  52   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  53   - INT and CR EXTRA svp64 fields completed.
  54 * SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
  55
  56 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  57
  58 * Lauri:
  59 * Jacob: C/C++ header for using SV through inline assembly
  60 * Cesar: TestIssuer FSM
  61 * Alain: power-gem5
  62 * Cole:
  63 * Luke: ISACaller, python-assembler-generator-class
  64 * Tobias:
  65 * Alexandre: binutils-svp64-assembler and gcc
  66 * Paul: microwatt
  67
  68 # Adding SV
  69
  70 order: listed in [[sv/overview]]
  71
  72 ## svp64 decoder
  73
  74 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  75
  76 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
  77 * power-gem5: TODO
  78 * TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
  79 * Microwatt: TODO, started auto-generated sv_decode.vhdl
  80 * python-based assembler-translator: 40% done (lkcl)
  81 * c++ macros: underway (jacob)
  82
  83 Note when decoding the RM into bits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
  84
  85 **IMPORTANT**! when spotting RA=0 in some instructions it is critical to note that the *full **seven** bits* are used (those from EXTRA2/3 included) because RA is no longer only five bits.
  86
  87 Links:
  88
  89 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  90 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  91 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD>
  92
  93 ## SVSTATE SPR needed
  94
  95 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  96
  97 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
  98
  99     num name    priv  width
 100     704,SVSTATE,no,no,32
 101     720,SVSRR0,yes,yes,32
 102
 103 Progress:
 104
 105 * ISACaller: done
 106 * power-gem5: TODO
 107 * TestIssuer: TODO
 108 * Microwatt: TODO
 109
 110 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 111
 112 ## Adding SVSTATE "set/get" support for hw/sw debugging
 113
 114 This includes adding DMI get/set support in hardware as well as gdb (remote) support.
 115
 116 * LibreSOC DMI/JTAG: TODO
 117 * Microwatt DMI: TODO
 118 * power-gem5 remote gdb: TODO
 119 * TestIssuer: DONE (read-only at least) <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=4d5482810c980ff927ccec62968a40a490ea86eb>
 120
 121 Links:
 122
 123 * <https://bugs.libre-soc.org/show_bug.cgi?id=609>
 124
 125 ## sv.setvl
 126
 127 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 128
 129 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 130 * ISACaller: TODO
 131 * power-gem5: TODO
 132 * TestIssuer: TODO
 133 * Microwatt: TODO
 134
 135 Links:
 136
 137 ## SVSRR0 for exceptions
 138
 139 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 140
 141 * ISACaller: TODO
 142 * power-gem5: TODO
 143 * TestIssuer: TODO
 144 * Microwatt: TODO
 145
 146 ## Illegal instruction exceptions
 147
 148 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 149
 150 * ISACaller: TODO
 151 * power-gem5: TODO
 152 * TestIssuer: TODO
 153 * Microwatt: TODO
 154
 155 ## VL for-loop
 156
 157 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 158
 159 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 160
 161 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 162
 163 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 164
 165 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 166 * power-gem5: TODO
 167 * TestIssuer:
 168   - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 169   - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
 170 * Microwatt: TODO
 171
 172 Remember the following register files need to have for-loops, plus
 173 unit tests:
 174
 175 * GPR
 176 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
 177 * Condition Registers.  see note below
 178 * FPR (if present)
 179
 180 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
 181
 182 ## Increasing register file sizes
 183
 184 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 185
 186 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 187
 188 ## Single and Twin Predication
 189
 190 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer
 191
 192 ## Element width overrides
 193
 194 TODO