openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  13 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  14
  15 # Code to convert
  16
  17 There are three projects:
  18
  19 * TestIssuer (the HDL)
  20 * ISACaller (the python-based simulator)
  21 * power-gem5 (a cycle accurate simulator)
  22
  23 Each of these needs to have SV augmentation, and the best way to
  24 do it is if they are all done at the same time, implementing the same
  25 incremental feature.
  26
  27 # Critical tasks
  28
  29 These are prerequisite tasks:
  30
  31 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  32   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  33   just use pygdbmi
  34   - needs remote gdb first https://github.com/gem5/gem5/blob/stable/src/arch/riscv/remote_gdb.cc
  35 * c++, c and python macros for generating [[sv/svp64]] assembler
  36   (svp64 prefixes)
  37
  38 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  39
  40 * Lauri:
  41 * Jacob: C/C++ header for using SV through inline assembly
  42 * Cesar: TestIssuer FSM
  43 * Alain: power-gem5
  44 * Cole:
  45 * Luke: ISACaller, python-assembler-generator-class
  46 * Tobias:
  47 * Alexandre: binutils-svp64-assembler
  48