openpower/sv/implementation.mdwn

   1 # Implementation
   2
   3 This page covers and coordinates implementing SV.  The basic concept is
   4 to go step-by-step through the [[sv/overview]] adding each feature,
   5 one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
   6
   7 Links:
   8
   9 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001865.html>
  10 * <https://bugs.libre-soc.org/show_bug.cgi?id=578> python-based svp64
  11   assembler translator
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=579> c/c++ macro svp64
  13   assembler translator
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=586> microwatt svp64-decode1.vhdl autogenerator
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
  16 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
  17   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
  18 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
  19 * <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
  20 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  21  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
  22 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
  23 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
  24 * <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
  25 * <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
  26
  27 # Code to convert
  28
  29 There are five projects:
  30
  31 * TestIssuer (the HDL)
  32 * ISACaller (the python-based simulator)
  33 * power-gem5 (a cycle accurate simulator)
  34 * Microwatt (VHDL)
  35 * gcc and binutils
  36
  37 Each of these needs to have SV augmentation, and the best way to
  38 do it is if they are all done at the same time, implementing the same
  39 incremental feature.
  40
  41 # Critical tasks
  42
  43 These are prerequisite tasks:
  44
  45 * power-gem5 automanagement, similar to pygdbmi for starting qemu
  46   - found this <https://www.gem5.org/documentation/general_docs/debugging_and_testing/debugging/debugging_simulated_code>
  47   just use pygdbmi
  48   - remote gdb should work <https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/remote_gdb.cc>
  49 * c++, c and python macros for generating [[sv/svp64]] assembler
  50   (svp64 prefixes)
  51   - python svp64 underway, minimalist sufficient for FU unit tests
  52 <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD>
  53 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
  54   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
  55   - INT and CR EXTRA svp64 fields completed.
  56 * SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
  57
  58 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
  59
  60 * Lauri:
  61 * Jacob: C/C++ header for using SV through inline assembly
  62 * Cesar: TestIssuer FSM
  63 * Alain: power-gem5
  64 * Cole:
  65 * Luke: ISACaller, python-assembler-generator-class
  66 * Tobias:
  67 * Alexandre: binutils-svp64-assembler and gcc
  68 * Paul: microwatt
  69
  70 # Adding SV
  71
  72 order: listed in [[sv/overview]]
  73
  74 ## svp64 decoder
  75
  76 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
  77
  78 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
  79 * power-gem5: TODO
  80 * TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
  81 * Microwatt: TODO, started auto-generated sv_decode.vhdl
  82 * python-based assembler-translator: 40% done (lkcl)
  83 * c++ macros: underway (jacob)
  84
  85 Note when decoding the RM into bits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
  86
  87 **IMPORTANT**! when spotting RA=0 in some instructions it is critical to note that the *full **seven** bits* are used (those from EXTRA2/3 included) because RA is no longer only five bits.
  88
  89 Links:
  90
  91 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
  92 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD>
  93 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD>
  94
  95 ## SVSTATE SPR needed
  96
  97 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
  98
  99 Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
 100
 101     num name    priv  width
 102     704,SVSTATE,no,no,32
 103     720,SVSRR0,yes,yes,32
 104
 105 Progress:
 106
 107 * ISACaller: done
 108 * power-gem5: TODO
 109 * TestIssuer: TODO
 110 * Microwatt: TODO
 111
 112 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 113
 114 ## Adding SVSTATE "set/get" support for hw/sw debugging
 115
 116 This includes adding DMI get/set support in hardware as well as gdb (remote) support.
 117
 118 * LibreSOC DMI/JTAG: TODO
 119 * Microwatt DMI: TODO
 120 * power-gem5 remote gdb: TODO
 121 * TestIssuer: DONE (read-only at least) <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=4d5482810c980ff927ccec62968a40a490ea86eb>
 122
 123 Links:
 124
 125 * <https://bugs.libre-soc.org/show_bug.cgi?id=609>
 126
 127 ## sv.setvl
 128
 129 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 130
 131 * LibreSOC OpenPOWER wiki fields/forms: DONE.  pseudocode: TODO
 132 * ISACaller: TODO
 133 * power-gem5: TODO
 134 * TestIssuer: TODO
 135 * Microwatt: TODO
 136
 137 Links:
 138
 139 ## SVSRR0 for exceptions
 140
 141 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 142
 143 * ISACaller: TODO
 144 * power-gem5: TODO
 145 * TestIssuer: TODO
 146 * Microwatt: TODO
 147
 148 ## Illegal instruction exceptions
 149
 150 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
 151
 152 * ISACaller: TODO
 153 * power-gem5: TODO
 154 * TestIssuer: TODO
 155 * Microwatt: TODO
 156
 157 ## VL for-loop
 158
 159 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
 160
 161 *This loop goes in between decode and issue phases*.  It is as if there were multiple sequential instructions in the instruction stream *and the loop must be treated as such*.  Specifically: all register read and write hazards **MUST** be respected; the Program Order must be respected even though and especially because this is Sub-PC execution.
 162
 163 This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must be used to store SVSTATE alongside when SRR0 and SRR1 store PC and MSR.
 164
 165 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 166
 167 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 168 * power-gem5: TODO
 169 * TestIssuer:
 170   - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 171   - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
 172 * Microwatt: TODO
 173
 174 Remember the following register files need to have for-loops, plus
 175 unit tests:
 176
 177 * GPR
 178 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
 179 * Condition Registers.  see note below
 180 * FPR (if present)
 181
 182 When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
 183
 184 ## Increasing register file sizes
 185
 186 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 187
 188 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 189
 190 ## Single and Twin Predication
 191
 192 both CR and INT predication is needed, as well as zeroing in both.
 193 the order is best done as follows:
 194
 195 * INT-based single
 196 * CR-based single
 197 * srcstep+dststep
 198 * INT-based twin
 199 * CR-based twin
 200 * Zeroing single
 201 * Zeroing twin
 202
 203 Best done as a FSM that "advances" srcstep and dststep over the
 204 zeros in their respective predicate masks, *including* when the
 205 src and dest predicate mask is "All 1s".
 206
 207 Bear in mind that srcstep+deststep are a form of back-to-back
 208 VGATHER+VSCATTER
 209
 210 Progress:
 211
 212 * TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617>
 213 * ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=618>
 214 * power-gem5: TODO
 215 * Microwatt: TODO
 216
 217 ## Element width overrides
 218
 219 TODO