3 # FPR-to-GPR and GPR-to-FPR
5 **Draft Status** under development, for submission as an RFC
9 * <https://bugs.libre-soc.org/show_bug.cgi?id=650>
10 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c71>
11 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c74>
12 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c76>
16 High-performance CPU/GPU software needs to often convert between integers
17 and floating-point, therefore fast conversion/data-movement instructions
18 are needed. Also given that initialisation of floats tends to take up
19 considerable space (even to just load 0.0) the inclusion of compact
20 format float immediate is up for consideration using BF16
22 Libre-SOC will be compliant with the
23 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,
24 and with its focus on modern 3D GPU hybrid workloads represents an
25 important new potential use-case for OpenPOWER.
27 Prior to the formation of the Compliancy Levels first introduced
29 the progressive historic development of the Scalar parts of the Power ISA assumed
30 that VSX would always be there to complement it. However With VMX/VSX
31 **not available** in the newly-introduced SFFS Compliancy Level, the
32 existing non-VSX conversion/data-movement instructions require load/store
33 instructions (slow and expensive) to transfer data between the FPRs and
34 the GPRs. For a 3D GPU this kills any modern competitive edge.
35 Also, because SimpleV needs efficient scalar instructions in
36 order to generate efficient vector instructions, adding new instructions
37 for data-transfer/conversion between FPRs and GPRs multiplies the savings.
39 In addition, the vast majority of GPR <-> FPR data-transfers are as part
40 of a FP <-> Integer conversion sequence, therefore reducing the number
41 of instructions required to the minimum seems necessary.
43 Therefore, we are proposing adding:
45 * FPR load-immediate using `BF16` as the constant
46 * FPR <-> GPR data-transfer instructions that just copy bits without conversion
47 * FPR <-> GPR combined data-transfer/conversion instructions that do
48 Integer <-> FP conversions
50 If we're adding new Integer <-> FP conversion instructions, we may
51 as well take this opportunity to modernise the instructions and make them
52 well suited for common/important conversion sequences:
54 * standard Integer -> FP IEEE754 conversion (used by most languages and CPUs)
55 * standard OpenPower FP -> Integer conversion (saturation with NaN
56 converted to minimum valid integer)
57 * Rust FP -> Integer conversion (saturation with NaN converted to 0)
58 * JavaScript FP -> Integer conversion (modular with Inf/NaN converted to 0)
60 The assembly listings in the [[int_fp_mv/appendix]] show how costly
61 some of these language-specific conversions are: Javascript is 35
62 scalar instructions, including four branches.
64 ## FP -> Integer conversions
66 Different programming languages turn out to have completely different
67 semantics for FP to Integer conversion. This section gives an overview
68 of the different variants, listing the languages and hardware that
69 implements each variant.
71 ## standard Integer -> FP conversion
73 This conversion is outlined in the IEEE754 specification. It is used
74 by nearly all programming languages and CPUs. In the case of OpenPOWER,
75 the rounding mode is read from FPSCR
77 ### standard OpenPower FP -> Integer conversion
79 This conversion, instead of exact IEEE754 Compliance, performs
80 "saturation with NaN converted to minimum valid integer". This
81 is also exactly the same as the x86 ISA conversion senantics.
82 OpenPOWER however has instructions for both:
84 * rounding mode read from FPSCR
85 * rounding mode always set to truncate
87 ### Rust FP -> Integer conversion
89 For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by Rust's `as` operator will be referred to as [Rust conversion semantics](#fp-to-int-rust-conversion-semantics).
91 Those same semantics are used in some way by all of the following languages (not necessarily for the default conversion method):
93 * Rust's FP -> Integer conversion using the
94 [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
96 [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
98 [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and
99 [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics
100 * SPIR-V's OpenCL dialect's
101 [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and
102 [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)
103 instructions when decorated with
104 [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).
106 ### JavaScript FP -> Integer conversion
108 For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by JavaScripts's `ToInt32` abstract operation will be referred to as [JavaScript conversion semantics](#fp-to-int-javascript-conversion-semantics).
110 This instruction is present in ARM assembler as FJCVTZS
111 <https://developer.arm.com/documentation/dui0801/g/hko1477562192868>
115 TODO: review and investigate other language semantics
117 # Proposed New Scalar Instructions
119 All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR. All integers however are sourced/stored in the *GPR*.
121 Integer operands and results being in the GPR is the key differentiator between the proposed instructions
122 (the entire rationale) compated to existing Scalar Power ISA.
123 In all existing Power ISA Scalar conversion instructions, all
124 operands are FPRs, even if the format of the source or destination
125 data is actually a scalar integer.
127 Note that source and destination widths can be overridden by SimpleV
128 SVP64, and that SVP64 also has Saturation Modes *in addition*
129 to those independently described here. SVP64 Overrides and Saturation
130 work on *both* Fixed *and* Floating Point operands and results.
131 The interactions with SVP64
132 are explained in the [[int_fp_mv/appendix]]
139 move a 64-bit float from a FPR to a GPR, just copying bits directly.
140 As a direct bitcopy, no exceptions occur and no status flags are set.
142 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
148 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the
149 64-bit float in `FRA` to a 32-bit float, then writes the 32-bit float to
150 `RT`. Effectively, `fmvtgs` is a macro-fusion of `frsp fmvtg`
151 and therefore has the exact same exception and flags behaviour of `frsp`
153 Unlike `frsp` however, with RT being a GPR, Rc=1 follows
154 standard *integer* behaviour, i.e. tests RT and sets CR0.
160 move a 64-bit float from a GPR to a FPR, just copying bits. No exceptions
161 are raised, no flags are altered of any kind.
163 Rc=1 tests FRT and sets CR1
167 move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
168 32-bit float in `RA` to a 64-bit float, then writes the 64-bit float to
169 `FRT`. Effectively, `fmvfgs` is a macro-fusion of `fmvfg frsp` and
170 therefore has the exact same exception and flags behaviour of `frsp`
172 Rc=1 tests FRT and sets CR1
174 TODO: clear statement on evaluation as to whether exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the conversion part. the semantics should really be the same as frsp)
176 v3.0C section 4.6.7.1 states:
178 FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.
180 Special Registers Altered:
185 ### Float load immediate (kinda a variant of `fmvfg`)
189 Reinterprets `FI << 16` as a 32-bit float, which is then converted to a
190 64-bit float and written to `FRT`. This is equivalent to reinterpreting
191 `FI` as a `BF16` and converting to 64-bit float.
193 There is no need for an Rc=1 variant because this is an immediate loading
194 instruction. This frees up one extra bit in the X-Form format for packing
201 fmvis f4, 0 # writes +0.0 to f4
202 # loading handy constants
203 fmvis f4, 0x8000 # writes -0.0 to f4
204 fmvis f4, 0x3F80 # writes +1.0 to f4
205 fmvis f4, 0xBF80 # writes -1.0 to f4
206 fmvis f4, 0xBFC0 # writes -1.5 to f4
207 fmvis f4, 0x7FC0 # writes +qNaN to f4
208 fmvis f4, 0x7F80 # writes +Infinity to f4
209 fmvis f4, 0xFF80 # writes -Infinity to f4
210 fmvis f4, 0x3FFF # writes +1.9921875 to f4
212 # clearing 128 FPRs with 2 SVP64 instructions
213 # by issuing 32 vec4 (subvector length 4) ops
215 sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
217 Important: If the float load immediate instruction(s) are left out,
218 change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
219 to instead write `+0.0` if `RA` is register `0`, at least
220 allowing clearing FPRs.
222 | 0-5 | 6-10 | 11-25 | 26-30 | 31 |
223 |--------|------|-------|-------|-----|
224 | Major | FRT | FI | XO | FI0 |
226 The above fits reasonably well with Minor 19 and follows the
227 pattern shown by `addpcis`, which uses an entire column of Minor 19
228 XO. 15 bits of FI fit into bits 11 to 25,
229 the top bit FI0 (MSB0 numbered 0) makes 16.
232 fp32 = bf16 || [0]*16
233 FRT = Single_to_Double(fp32)
235 ## FPR to GPR conversions
237 <div id="fpr-to-gpr-conversion-mode"></div>
241 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 |
242 |--------|------|--------|-------|-------|----|
243 | Major | RT | //Mode | FRA | XO | Rc |
244 | Major | FRT | //Mode | RA | XO | Rc |
248 | Mode | `rounding_mode` | Semantics |
249 |------|-----------------|----------------------------------|
250 | 000 | from `FPSCR` | [OpenPower semantics] |
251 | 001 | Truncate | [OpenPower semantics] |
252 | 010 | from `FPSCR` | [Rust semantics] |
253 | 011 | Truncate | [Rust semantics] |
254 | 100 | from `FPSCR` | [JavaScript semantics] |
255 | 101 | Truncate | [JavaScript semantics] |
256 | rest | -- | illegal instruction trap for now |
258 [OpenPower semantics]: #fp-to-int-openpower-conversion-semantics
259 [Rust semantics]: #fp-to-int-rust-conversion-semantics
260 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics
262 `fcvttgw RT, FRA, Mode`
264 Convert from 64-bit float to 32-bit signed integer, writing the result
265 to the GPR `RT`. Converts using [mode `Mode`]
267 `fcvttguw RT, FRA, Mode`
269 Convert from 64-bit float to 32-bit unsigned integer, writing the result
270 to the GPR `RT`. Converts using [mode `Mode`]
272 `fcvttgd RT, FRA, Mode`
274 Convert from 64-bit float to 64-bit signed integer, writing the result
275 to the GPR `RT`. Converts using [mode `Mode`]
277 `fcvttgud RT, FRA, Mode`
279 Convert from 64-bit float to 64-bit unsigned integer, writing the result
280 to the GPR `RT`. Converts using [mode `Mode`]
282 `fcvtstgw RT, FRA, Mode`
284 Convert from 32-bit float to 32-bit signed integer, writing the result
285 to the GPR `RT`. Converts using [mode `Mode`]
287 `fcvtstguw RT, FRA, Mode`
289 Convert from 32-bit float to 32-bit unsigned integer, writing the result
290 to the GPR `RT`. Converts using [mode `Mode`]
292 `fcvtstgd RT, FRA, Mode`
294 Convert from 32-bit float to 64-bit signed integer, writing the result
295 to the GPR `RT`. Converts using [mode `Mode`]
297 `fcvtstgud RT, FRA, Mode`
299 Convert from 32-bit float to 64-bit unsigned integer, writing the result
300 to the GPR `RT`. Converts using [mode `Mode`]
302 [mode `Mode`]: #fpr-to-gpr-conversion-mode
304 ## GPR to FPR conversions
306 All of the following GPR to FPR conversions use the rounding mode from `FPSCR`.
310 Convert from 32-bit signed integer in the GPR `RA` to 64-bit float in `FRT`.
314 Convert from 32-bit signed integer in the GPR `RA` to 32-bit float in `FRT`.
318 Convert from 32-bit unsigned integer in the GPR `RA` to 64-bit float in `FRT`.
322 Convert from 32-bit unsigned integer in the GPR `RA` to 32-bit float in `FRT`.
326 Convert from 64-bit signed integer in the GPR `RA` to 64-bit float in `FRT`.
330 Convert from 64-bit signed integer in the GPR `RA` to 32-bit float in `FRT`.
334 Convert from 64-bit unsigned integer in the GPR `RA` to 64-bit float in `FRT`.
338 Convert from 64-bit unsigned integer in the GPR `RA` to 32-bit float in `FRT`.
340 # FP to Integer Conversion Pseudo-code
344 | term | result type | definition |
345 |---------------------------|-------------|----------------------------------------------------------------------------------------------------|
346 | `fp` | -- | `f32` or `f64` (or other types from SimpleV) |
347 | `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) |
348 | `uint` | -- | the unsigned integer of the same bit-width as `int` |
349 | `int::BITS` | `int` | the bit-width of `int` |
350 | `int::MIN_VALUE` | `int` | the minimum value `int` can store (`0` if unsigned, `-2^(int::BITS-1)` if signed) |
351 | `int::MAX_VALUE` | `int` | the maximum value `int` can store (`2^int::BITS - 1` if unsigned, `2^(int::BITS-1) - 1` if signed) |
352 | `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. |
353 | `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
355 <div id="fp-to-int-openpower-conversion-semantics"></div>
356 OpenPower conversion semantics (section A.2 page 999 (page 1023) of OpenPower ISA v3.1):
359 def fp_to_int_open_power<fp, int>(v: fp) -> int:
361 return int::MIN_VALUE
362 if v >= int::MAX_VALUE:
363 return int::MAX_VALUE
364 if v <= int::MIN_VALUE:
365 return int::MIN_VALUE
366 return (int)rint(v, rounding_mode)
369 <div id="fp-to-int-rust-conversion-semantics"></div>
370 Rust [conversion semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics) (with adjustment to add non-truncate rounding modes):
373 def fp_to_int_rust<fp, int>(v: fp) -> int:
376 if v >= int::MAX_VALUE:
377 return int::MAX_VALUE
378 if v <= int::MIN_VALUE:
379 return int::MIN_VALUE
380 return (int)rint(v, rounding_mode)
383 <div id="fp-to-int-javascript-conversion-semantics"></div>
384 Section 7.1 of the ECMAScript / JavaScript
385 [conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32) (with adjustment to add non-truncate rounding modes):
388 def fp_to_int_java_script<fp, int>(v: fp) -> int:
389 if v is NaN or infinite:
391 v = rint(v, rounding_mode)
392 v = v mod int::VALUE_COUNT # 2^32 for i32, 2^64 for i64, result is non-negative
397 # Equivalent OpenPower ISA v3.0 Assembly Language for FP -> Integer Conversion Modes
399 Moved to [[int_fp_mv/appendix]]