3 Note on considered alternative naming schemes: we decided to switch to using the reduced mnemonic naming scheme (over some people's objections) since it would be 5 instructions instead of dozens, though we did consider trying to match PowerISA's existing naming scheme for the instructions rather than only for the instruction aliases. <https://bugs.libre-soc.org/show_bug.cgi?id=1015#c7>
5 # FPR-to-GPR and GPR-to-FPR
7 TODO special constants instruction (e, tau/N, ln 2, sqrt 2, etc.) -- exclude any constants available through fmvis
9 **Draft Status** under development, for submission as an RFC
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=650>
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c71>
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c74>
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c76>
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=887> fmvis
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=1015> int-fp RFC
19 * [[int_fp_mv/appendix]]
20 * [[sv/rfc/ls002]] - `fmvis` and `fishmv` External RFC Formal Submission
21 * [[sv/rfc/ls006]] - int-fp-mv External RFC Formal Submission
25 * Rust is a Trademark of the Rust Foundation
26 * Java and JavaScript are Trademarks of Oracle
27 * LLVM is a Trademark of the LLVM Foundation
28 * SPIR-V is a Trademark of the Khronos Group
29 * OpenCL is a Trademark of Apple, Inc.
31 Referring to these Trademarks within this document
32 is by necessity, in order to put the semantics of each language
33 into context, and is considered "fair use" under Trademark
38 High-performance CPU/GPU software needs to often convert between integers
39 and floating-point, therefore fast conversion/data-movement instructions
40 are needed. Also given that initialisation of floats tends to take up
41 considerable space (even to just load 0.0) the inclusion of two compact
42 format float immediate instructions is up for consideration using 16-bit
43 immediates. BF16 is one of the formats: a second instruction allows a full
44 accuracy FP32 to be constructed.
46 Libre-SOC will be compliant with the
47 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,
48 and with its focus on modern 3D GPU hybrid workloads represents an
49 important new potential use-case for OpenPOWER.
51 Prior to the formation of the Compliancy Levels first introduced
53 the progressive historic development of the Scalar parts of the Power ISA assumed
54 that VSX would always be there to complement it. However With VMX/VSX
55 **not available** in the newly-introduced SFFS Compliancy Level, the
56 existing non-VSX conversion/data-movement instructions require
57 a Vector of load/store
58 instructions (slow and expensive) to transfer data between the FPRs and
59 the GPRs. For a modern 3D GPU this kills any possibility of a
61 Also, because SimpleV needs efficient scalar instructions in
62 order to generate efficient vector instructions, adding new instructions
63 for data-transfer/conversion between FPRs and GPRs multiplies the savings.
65 In addition, the vast majority of GPR <-> FPR data-transfers are as part
66 of a FP <-> Integer conversion sequence, therefore reducing the number
67 of instructions required is a priority.
69 Therefore, we are proposing adding:
71 * FPR load-immediate instructions, one equivalent to `BF16`, the
72 other increasing accuracy to `FP32`
73 * FPR <-> GPR data-transfer instructions that just copy bits without conversion
74 * FPR <-> GPR combined data-transfer/conversion instructions that do
75 Integer <-> FP conversions
77 If adding new Integer <-> FP conversion instructions,
78 the opportunity may be taken to modernise the instructions and make them
79 well-suited for common/important conversion sequences:
82 * **standard IEEE754** - used by most languages and CPUs
84 * **standard OpenPOWER** - saturation with NaN
85 converted to minimum valid integer
86 * **Java/Saturating** - saturation with NaN converted to 0
87 * **JavaScript** - modulo wrapping with Inf/NaN converted to 0
89 The assembly listings in the [[int_fp_mv/appendix]] show how costly
90 some of these language-specific conversions are: JavaScript, the
91 worst case, is 32 scalar instructions including seven branch instructions.
92 (FIXME: disagrees with ls006 and sv.mdwn)
94 # Proposed New Scalar Instructions
96 All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR. All integers however are sourced/stored in the *GPR*.
98 Integer operands and results being in the GPR is the key differentiator between the proposed instructions
99 (the entire rationale) compared to existing Scalar Power ISA.
100 In all existing Power ISA Scalar conversion instructions, all
101 operands are FPRs, even if the format of the source or destination
102 data is actually a scalar integer.
104 *(The existing Scalar instructions being FP-FP only is based on an assumption
105 that VSX will be implemented, and VSX is not part of the SFFS Compliancy
106 Level. An earlier version of the Power ISA used to have similar
107 FPR<->GPR instructions to these:
108 they were deprecated due to this incorrect assumption that VSX would
111 Note that source and destination widths can be overridden by SimpleV
112 SVP64, and that SVP64 also has Saturation Modes *in addition*
113 to those independently described here. SVP64 Overrides and Saturation
114 work on *both* Fixed *and* Floating Point operands and results.
115 The interactions with SVP64
116 are explained in the [[int_fp_mv/appendix]]
118 # Float load immediate <a name="fmvis"></a>
120 These are like a variant of `fmvfg` and `oris`, combined.
121 Power ISA currently requires a large
122 number of instructions to get Floating Point constants into registers.
123 `fmvis` on its own is equivalent to BF16 to FP32/64 conversion,
124 but if followed up by `fishmv` an additional 16 bits of accuracy in the
125 mantissa may be achieved.
127 These instructions **always** save
128 resources compared to FP-load for exactly the same reason
129 that `li` saves resources: an L1-Data-Cache and memory read
132 *IBM may consider it worthwhile to extend these two instructions to
133 v3.1 Prefixed (`pfmvis` and `pfishmv`: 8RR, imm0 extended).
134 If so it is recommended that
135 `pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high
136 missing exponent bits (numbered 8 to 10) and the lower additional
137 29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.
138 Strictly speaking the sequence `fmvis fishmv pfishmv` achieves the
139 same effect in the same number of bytes as `pfmvis pfishmv`,
140 making `pfmvis` redundant.*
142 Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv.
143 As fishmv is specifically intended to work in conjunction with fmvis
144 to provide additional accuracy, all bits other than those which
145 would have been set by a prior fmvis instruction are deliberately ignored.
146 (If these instructions involved reading from registers rather than immediates
147 it would be a different story).
149 ## Load BF16 Immediate
153 Reinterprets `D << 16` as a 32-bit float, which is then converted to a
154 64-bit float and written to `FRS`. This is equivalent to reinterpreting
155 `D` as a `BF16` and converting to 64-bit float.
156 There is no need for an Rc=1 variant because this is an immediate loading
163 fmvis f4, 0 # writes +0.0 to f4
164 # loading handy constants
165 fmvis f4, 0x8000 # writes -0.0 to f4
166 fmvis f4, 0x3F80 # writes +1.0 to f4
167 fmvis f4, 0xBF80 # writes -1.0 to f4
168 fmvis f4, 0xBFC0 # writes -1.5 to f4
169 fmvis f4, 0x7FC0 # writes +qNaN to f4
170 fmvis f4, 0x7F80 # writes +Infinity to f4
171 fmvis f4, 0xFF80 # writes -Infinity to f4
172 fmvis f4, 0x3FFF # writes +1.9921875 to f4
174 # clearing 128 FPRs with 2 SVP64 instructions
175 # by issuing 32 vec4 (subvector length 4) ops
177 sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
179 Important: If the float load immediate instruction(s) are left out,
180 change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
181 to instead write `+0.0` if `RA` is register `0`, at least
182 allowing clearing FPRs.
184 `fmvis` fits with DX-Form:
186 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |
187 |--------|------|-------|-------|-------|-----|---------|
188 | Major | FRS | d1 | d0 | XO | d2 | DX-Form |
192 bf16 = d0 || d1 || d2 # create BF16 immediate
193 fp32 = bf16 || [0]*16 # convert BF16 to FP32
194 FRS = DOUBLE(fp32) # convert FP32 to FP64
196 Special registers altered:
200 ## Float Immediate Second-Half MV <a name="fishmv"></a>
206 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |
207 |--------|------|-------|-------|-------|-----|---------|
208 | Major | FRS | d1 | d0 | XO | d2 | DX-Form |
210 Strategically similar to how `oris` is used to construct
211 32-bit Integers, an additional 16-bits of immediate is
212 inserted into `FRS` to extend its accuracy to
213 a full FP32 (stored as usual in FP64 Format within the FPR).
214 If a prior `fmvis` instruction had been used to
215 set the upper 16-bits of an FP32 value, `fishmv` contains the
218 The key difference between using `li` and `oris` to construct 32-bit
219 GPR Immediates and `fishmv` is that the `fmvis` will have converted
220 the `BF16` immediate to FP64 (Double) format.
221 This is taken into consideration
222 as can be seen in the pseudocode below.
226 fp32 <- SINGLE((FRS)) # convert to FP32
227 fp32[16:31] <- d0 || d1 || d2 # replace LSB half
228 FRS <- DOUBLE(fp32) # convert back to FP64
230 Special registers altered:
234 **This instruction performs a Read-Modify-Write.** *FRS is read, the additional
235 16 bit immediate inserted, and the result also written to FRS*
240 # these two combined instructions write 0x3f808000
241 # into f4 as an FP32 to be converted to an FP64.
242 # actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
243 # first the upper bits, happens to be +1.0
244 fmvis f4, 0x3F80 # writes +1.0 to f4
245 # now write the lower 16 bits of an FP32
246 fishmv f4, 0x8000 # writes +1.00390625 to f4
251 Tables that are used by
252 `fmvtg[s][.]`/`fmvfg[s][.]`/`fcvttg[s][.]`/`fcvtfg[s][.]`:
254 ## `RCS` -- `Rc` and `s`
256 | `RCS` | `Rc` | FP Single Mode | Assembly Alias Mnemonic |
257 |-------|------|----------------|-------------------------|
258 | 0 | 0 | Double | `<op>` |
259 | 1 | 1 | Double | `<op>.` |
260 | 2 | 0 | Single | `<op>s` |
261 | 3 | 1 | Single | `<op>s.` |
263 ## `IT` -- Integer Type
265 | `IT` | Integer Type | Assembly Alias Mnemonic |
266 |------|-----------------|-------------------------|
267 | 0 | Signed 32-bit | `<op>w` |
268 | 1 | Unsigned 32-bit | `<op>uw` |
269 | 2 | Signed 64-bit | `<op>d` |
270 | 3 | Unsigned 64-bit | `<op>ud` |
272 ## `CVM` -- Float to Integer Conversion Mode
274 | `CVM` | `rounding_mode` | Semantics |
275 |-------|-----------------|----------------------------------|
276 | 000 | from `FPSCR` | [OpenPower semantics] |
277 | 001 | Truncate | [OpenPower semantics] |
278 | 010 | from `FPSCR` | [Java/Saturating semantics] |
279 | 011 | Truncate | [Java/Saturating semantics] |
280 | 100 | from `FPSCR` | [JavaScript semantics] |
281 | 101 | Truncate | [JavaScript semantics] |
282 | rest | -- | illegal instruction trap for now |
284 [OpenPower semantics]: #fp-to-int-openpower-conversion-semantics
285 [Java/Saturating semantics]: #fp-to-int-java-saturating-conversion-semantics
286 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics
290 These instructions perform a straight unaltered bit-level copy from one Register
293 ## Floating Move To GPR
300 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form |
301 |-----|------|-------|-------|-------|----|--------|
302 | PO | RT | 0 | FRB | XO | Rc | X-Form |
308 Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754
309 representation directly. This is equivalent to `stfd` followed by `ld`.
310 As `fmvtg` is just copying bits, `FPSCR` is not affected in any way.
312 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
315 Special Registers altered:
319 ## Floating Move To GPR Single
326 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form |
327 |-----|------|-------|-------|-------|----|--------|
328 | PO | RT | 0 | FRB | XO | Rc | X-Form |
331 RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses
334 Move a 32-bit float from a FPR to a GPR, just copying bits of the IEEE 754
335 representation directly. This is equivalent to `stfs` followed by `lwz`.
336 As `fmvtgs` is just copying bits, `FPSCR` is not affected in any way.
338 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
341 Special Registers altered:
345 ## Floating Move From GPR
352 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form |
353 |-----|------|-------|-------|-------|----|--------|
354 | PO | FRT | 0 | RB | XO | Rc | X-Form |
360 move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754
361 representation directly. This is equivalent to `std` followed by `lfd`.
362 As `fmvfg` is just copying bits, `FPSCR` is not affected in any way.
364 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
367 Special Registers altered:
371 ## Floating Move From GPR Single
378 | 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form |
379 |-----|------|-------|-------|-------|----|--------|
380 | PO | FRT | 0 | RB | XO | Rc | X-Form |
383 FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses
386 move a 32-bit float from a GPR to a FPR, just copying bits of the IEEE 754
387 representation directly. This is equivalent to `stw` followed by `lfs`.
388 As `fmvfgs` is just copying bits, `FPSCR` is not affected in any way.
390 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
393 Special Registers altered:
399 Unlike the move instructions
400 these instructions perform conversions between Integer and
401 Floating Point. Truncation can therefore occur, as well
404 ## Floating Convert From Integer In GPR
406 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form |
407 |-----|------|-------|-------|-------|-------|----|--------|
408 | PO | FRT | IT | 0 | RB | XO | Rc | X-Form |
416 if IT[0] = 0 then # 32-bit int -> 64-bit float
417 # rounding never necessary, so don't touch FPSCR
418 # based off xvcvsxwdp
419 if IT = 0 then # Signed 32-bit
420 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
421 else # IT = 1 -- Unsigned 32-bit
422 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
423 FRT <- bfp64_CONVERT_FROM_BFP(src)
425 # rounding may be necessary. based off xscvuxdsp
428 case(0): # Signed 32-bit
429 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
430 case(1): # Unsigned 32-bit
431 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
432 case(2): # Signed 64-bit
433 src <- bfp_CONVERT_FROM_SI64((RB))
434 default: # Unsigned 64-bit
435 src <- bfp_CONVERT_FROM_UI64((RB))
436 rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
437 result <- bfp64_CONVERT_FROM_BFP(rnd)
438 cls <- fprf_CLASS_BFP64(result)
440 if xx_flag = 1 then SetFX(FPSCR.XX)
447 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
448 don't remove them -->
450 Convert from a unsigned/signed 32/64-bit integer in RB to a 64-bit
453 If converting from a unsigned/signed 32-bit integer to a 64-bit float,
454 rounding is never necessary, so `FPSCR` is unmodified and exceptions are
455 never raised. Otherwise, `FPSCR` is modified and exceptions are raised
458 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
461 Special Registers altered:
464 FPCSR (TODO: which bits?) (if IT[0]=1)
468 | Assembly Alias | Full Instruction | | Assembly Alias | Full Instruction |
469 |----------------------|----------------------|------|----------------------|----------------------|
470 | `fcvtfgw FRT, RB` | `fcvtfg FRT, RB, 0` | | `fcvtfgd FRT, RB` | `fcvtfg FRT, RB, 2` |
471 | `fcvtfgw. FRT, RB` | `fcvtfg. FRT, RB, 0` | | `fcvtfgd. FRT, RB` | `fcvtfg. FRT, RB, 2` |
472 | `fcvtfguw FRT, RB` | `fcvtfg FRT, RB, 1` | | `fcvtfgud FRT, RB` | `fcvtfg FRT, RB, 3` |
473 | `fcvtfguw. FRT, RB` | `fcvtfg. FRT, RB, 1` | | `fcvtfgud. FRT, RB` | `fcvtfg. FRT, RB, 3` |
475 ## Floating Convert From Integer In GPR Single
477 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-30 | 31 | Form |
478 |-----|------|-------|-------|-------|-------|----|--------|
479 | PO | FRT | IT | 0 | RB | XO | Rc | X-Form |
487 # rounding may be necessary. based off xscvuxdsp
490 case(0): # Signed 32-bit
491 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
492 case(1): # Unsigned 32-bit
493 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
494 case(2): # Signed 64-bit
495 src <- bfp_CONVERT_FROM_SI64((RB))
496 default: # Unsigned 64-bit
497 src <- bfp_CONVERT_FROM_UI64((RB))
498 rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
499 result32 <- bfp32_CONVERT_FROM_BFP(rnd)
500 cls <- fprf_CLASS_BFP32(result32)
501 result <- DOUBLE(result32)
503 if xx_flag = 1 then SetFX(FPSCR.XX)
510 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
511 don't remove them -->
513 Convert from a unsigned/signed 32/64-bit integer in RB to a 32-bit
514 float in FRT, following the usual 32-bit float in 64-bit float format.
515 `FPSCR` is modified and exceptions are raised as usual.
517 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
520 Special Registers altered:
523 FPCSR (TODO: which bits?)
527 | Assembly Alias | Full Instruction | | Assembly Alias | Full Instruction |
528 |----------------------|----------------------|------|----------------------|----------------------|
529 | `fcvtfgws FRT, RB` | `fcvtfg FRT, RB, 0` | | `fcvtfgds FRT, RB` | `fcvtfg FRT, RB, 2` |
530 | `fcvtfgws. FRT, RB` | `fcvtfg. FRT, RB, 0` | | `fcvtfgds. FRT, RB` | `fcvtfg. FRT, RB, 2` |
531 | `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1` | | `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3` |
532 | `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` | | `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` |
534 ## Floating-point to Integer Conversion Overview
536 <div id="fpr-to-gpr-conversion-mode"></div>
538 IEEE 754 doesn't specify what results are obtained when converting a NaN
539 or out-of-range floating-point value to integer, so different programming
540 languages and ISAs have made different choices. Below is an overview
541 of the different variants, listing the languages and hardware that
542 implements each variant.
544 For convenience, we will give those different conversion semantics names
545 based on which common ISA or programming language uses them, since there
546 may not be an established name for them:
548 **Standard OpenPower conversion**
550 This conversion performs "saturation with NaN converted to minimum
551 valid integer". This is also exactly the same as the x86 ISA conversion
552 semantics. OpenPOWER however has instructions for both:
554 * rounding mode read from FPSCR
555 * rounding mode always set to truncate
557 **Java/Saturating conversion**
559 For the sake of simplicity, the FP -> Integer conversion semantics
560 generalized from those used by Java's semantics (and Rust's `as`
561 operator) will be referred to as [Java/Saturating conversion
562 semantics](#fp-to-int-java-saturating-conversion-semantics).
564 Those same semantics are used in some way by all of the following
565 languages (not necessarily for the default conversion method):
568 [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
569 (only for long/int results)
570 * Rust's FP -> Integer conversion using the
571 [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
573 [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and
574 [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics
575 * SPIR-V's OpenCL dialect's
576 [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and
577 [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)
578 instructions when decorated with
579 [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).
580 * WebAssembly has also introduced
581 [trunc_sat_u](ttps://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-u) and
582 [trunc_sat_s](https://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-s)
584 **JavaScript conversion**
586 For the sake of simplicity, the FP -> Integer conversion
587 semantics generalized from those used by JavaScripts's `ToInt32`
588 abstract operation will be referred to as [JavaScript conversion
589 semantics](#fp-to-int-javascript-conversion-semantics).
591 This instruction is present in ARM assembler as FJCVTZS
592 <https://developer.arm.com/documentation/dui0801/g/hko1477562192868>
596 All of these instructions have an Rc=1 mode which sets CR0
597 in the normal way for any instructions producing a GPR result.
598 Additionally, when OE=1, if the numerical value of the FP number
599 is not 100% accurately preserved (due to truncation or saturation
600 and including when the FP number was NaN) then this is considered
601 to be an integer Overflow condition, and CR0.SO, XER.SO and XER.OV
602 are all set as normal for any GPR instructions that overflow.
604 ### FP to Integer Conversion Simplified Pseudo-code
608 | term | result type | definition |
609 |---------------------------|-------------|----------------------------------------------------------------------------------------------------|
610 | `fp` | -- | `f32` or `f64` (or other types from SimpleV) |
611 | `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) |
612 | `uint` | -- | the unsigned integer of the same bit-width as `int` |
613 | `int::BITS` | `int` | the bit-width of `int` |
614 | `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` |
615 | `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` |
616 | `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` |
617 | `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` |
618 | `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. |
619 | `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
621 <div id="fp-to-int-openpower-conversion-semantics"></div>
622 OpenPower conversion semantics (section A.2 page 1009 (page 1035) of
626 def fp_to_int_open_power<fp, int>(v: fp) -> int:
628 return int::MIN_VALUE
629 if v >= int::MAX_VALUE:
630 return int::MAX_VALUE
631 if v <= int::MIN_VALUE:
632 return int::MIN_VALUE
633 return (int)rint(v, rounding_mode)
636 <div id="fp-to-int-java-saturating-conversion-semantics"></div>
637 [Java/Saturating conversion semantics](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
638 (only for long/int results)/
639 [Rust semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
640 (with adjustment to add non-truncate rounding modes):
643 def fp_to_int_java_saturating<fp, int>(v: fp) -> int:
646 if v >= int::MAX_VALUE:
647 return int::MAX_VALUE
648 if v <= int::MIN_VALUE:
649 return int::MIN_VALUE
650 return (int)rint(v, rounding_mode)
653 <div id="fp-to-int-javascript-conversion-semantics"></div>
654 Section 7.1 of the ECMAScript / JavaScript
655 [conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32)
656 (with adjustment to add non-truncate rounding modes):
659 def fp_to_int_java_script<fp, int>(v: fp) -> int:
660 if v is NaN or infinite:
662 v = rint(v, rounding_mode) # assume no loss of precision in result
663 v = v mod int::VALUE_COUNT # 2^32 for i32, 2^64 for i64, result is non-negative
668 ## Floating Convert To Integer In GPR
670 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30 | 31 | Form |
671 |-----|------|-------|-------|-------|-------|----|----|---------|
672 | PO | RT | IT | CVM | FRB | XO | OE | Rc | XO-Form |
675 fcvttg RT, FRB, CVM, IT
676 fcvttg. RT, FRB, CVM, IT
677 fcvttgo RT, FRB, CVM, IT
678 fcvttgo. RT, FRB, CVM, IT
682 # based on xscvdpuxws
684 src <- bfp_CONVERT_FROM_BFP64((FRB))
687 case(0): # Signed 32-bit
688 range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
689 range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
690 js_mask <- 0xFFFF_FFFF
691 case(1): # Unsigned 32-bit
692 range_min <- bfp_CONVERT_FROM_UI32(0)
693 range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
694 js_mask <- 0xFFFF_FFFF
695 case(2): # Signed 64-bit
696 range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
697 range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
698 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
699 default: # Unsigned 64-bit
700 range_min <- bfp_CONVERT_FROM_UI64(0)
701 range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
702 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
704 if CVM[2] = 1 or FPSCR.RN = 0b01 then
705 rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
706 else if FPSCR.RN = 0b00 then
707 rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
708 else if FPSCR.RN = 0b10 then
709 rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
710 else if FPSCR.RN = 0b11 then
711 rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
714 case(0, 1): # OpenPower semantics
716 result <- si64_CONVERT_FROM_BFP(range_min)
717 else if bfp_COMPARE_GT(rnd, range_max) then
718 result <- ui64_CONVERT_FROM_BFP(range_max)
719 else if bfp_COMPARE_LT(rnd, range_min) then
720 result <- si64_CONVERT_FROM_BFP(range_min)
721 else if IT[1] = 1 then # Unsigned 32/64-bit
722 result <- ui64_CONVERT_FROM_BFP(range_max)
723 else # Signed 32/64-bit
724 result <- si64_CONVERT_FROM_BFP(range_max)
725 case(2, 3): # Java/Saturating semantics
728 else if bfp_COMPARE_GT(rnd, range_max) then
729 result <- ui64_CONVERT_FROM_BFP(range_max)
730 else if bfp_COMPARE_LT(rnd, range_min) then
731 result <- si64_CONVERT_FROM_BFP(range_min)
732 else if IT[1] = 1 then # Unsigned 32/64-bit
733 result <- ui64_CONVERT_FROM_BFP(range_max)
734 else # Signed 32/64-bit
735 result <- si64_CONVERT_FROM_BFP(range_max)
736 default: # JavaScript semantics
737 # CVM = 6, 7 are illegal instructions
738 # this works because the largest type we try to convert from has
739 # 53 significand bits, and the largest type we try to convert to
740 # has 64 bits, and the sum of those is strictly less than the 128
741 # bits of the intermediate result.
742 limit <- bfp_CONVERT_FROM_UI128([1] * 128)
743 if IsInf(rnd) or IsNaN(rnd) then
745 else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
748 result128 <- si128_CONVERT_FROM_BFP(rnd)
749 result <- result128[64:127] & js_mask
752 case(0): # Signed 32-bit
753 result <- EXTS64(result[32:63])
754 result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
755 case(1): # Unsigned 32-bit
756 result <- EXTZ64(result[32:63])
757 result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
758 case(2): # Signed 64-bit
759 result_bfp <- bfp_CONVERT_FROM_SI64(result)
760 default: # Unsigned 64-bit
761 result_bfp <- bfp_CONVERT_FROM_UI64(result)
763 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
764 if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
765 if xx_flag = 1 then SetFX(FPSCR.XX)
767 vx_flag <- vxsnan_flag | vxcvi_flag
768 vex_flag <- FPSCR.VE & vx_flag
772 FPSCR.FPRF <- undefined
775 if IsNaN(src) or not bfp_COMPARE_EQ(src, result_bfp) then
776 overflow <- 1 # signals SO only when OE = 1
782 Convert from 64-bit float in FRB to a unsigned/signed 32/64-bit integer
783 in RT, with the conversion overflow/rounding semantics following the
784 chosen `CVM` value. `FPSCR` is modified and exceptions are raised as usual.
786 These instructions have an Rc=1 mode which sets CR0 in the normal
787 way for any instructions producing a GPR result. Additionally, when OE=1,
788 if the numerical value of the FP number is not 100% accurately preserved
789 (due to truncation or saturation and including when the FP number was
790 NaN) then this is considered to be an Integer Overflow condition, and
791 CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
794 Special Registers altered:
797 XER SO, OV, OV32 (if OE=1)
798 FPCSR (TODO: which bits?)
802 | Assembly Alias | Full Instruction | Assembly Alias | Full Instruction |
803 |---------------------------|----------------------------|---------------------------|----------------------------|
804 | `fcvttgw RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 0` | `fcvttgd RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 2` |
805 | `fcvttgw. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 0` | `fcvttgd. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 2` |
806 | `fcvttgwo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 0` | `fcvttgdo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 2` |
807 | `fcvttgwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 0` | `fcvttgdo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 2` |
808 | `fcvttguw RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 1` | `fcvttgud RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 3` |
809 | `fcvttguw. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 1` | `fcvttgud. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 3` |
810 | `fcvttguwo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 1` | `fcvttgudo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 3` |
811 | `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` | `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
813 ## Floating Convert Single To Integer In GPR
815 | 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30 | 31 | Form |
816 |-----|------|-------|-------|-------|-------|----|----|---------|
817 | PO | RT | IT | CVM | FRB | XO | OE | Rc | XO-Form |
820 fcvtstg RT, FRB, CVM, IT
821 fcvtstg. RT, FRB, CVM, IT
822 fcvtstgo RT, FRB, CVM, IT
823 fcvtstgo. RT, FRB, CVM, IT
827 # based on xscvdpuxws
829 src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
832 case(0): # Signed 32-bit
833 range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
834 range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
835 js_mask <- 0xFFFF_FFFF
836 case(1): # Unsigned 32-bit
837 range_min <- bfp_CONVERT_FROM_UI32(0)
838 range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
839 js_mask <- 0xFFFF_FFFF
840 case(2): # Signed 64-bit
841 range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
842 range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
843 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
844 default: # Unsigned 64-bit
845 range_min <- bfp_CONVERT_FROM_UI64(0)
846 range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
847 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
849 if CVM[2] = 1 or FPSCR.RN = 0b01 then
850 rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
851 else if FPSCR.RN = 0b00 then
852 rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
853 else if FPSCR.RN = 0b10 then
854 rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
855 else if FPSCR.RN = 0b11 then
856 rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
859 case(0, 1): # OpenPower semantics
861 result <- si64_CONVERT_FROM_BFP(range_min)
862 else if bfp_COMPARE_GT(rnd, range_max) then
863 result <- ui64_CONVERT_FROM_BFP(range_max)
864 else if bfp_COMPARE_LT(rnd, range_min) then
865 result <- si64_CONVERT_FROM_BFP(range_min)
866 else if IT[1] = 1 then # Unsigned 32/64-bit
867 result <- ui64_CONVERT_FROM_BFP(range_max)
868 else # Signed 32/64-bit
869 result <- si64_CONVERT_FROM_BFP(range_max)
870 case(2, 3): # Java/Saturating semantics
873 else if bfp_COMPARE_GT(rnd, range_max) then
874 result <- ui64_CONVERT_FROM_BFP(range_max)
875 else if bfp_COMPARE_LT(rnd, range_min) then
876 result <- si64_CONVERT_FROM_BFP(range_min)
877 else if IT[1] = 1 then # Unsigned 32/64-bit
878 result <- ui64_CONVERT_FROM_BFP(range_max)
879 else # Signed 32/64-bit
880 result <- si64_CONVERT_FROM_BFP(range_max)
881 default: # JavaScript semantics
882 # CVM = 6, 7 are illegal instructions
883 # this works because the largest type we try to convert from has
884 # 53 significand bits, and the largest type we try to convert to
885 # has 64 bits, and the sum of those is strictly less than the 128
886 # bits of the intermediate result.
887 limit <- bfp_CONVERT_FROM_UI128([1] * 128)
888 if IsInf(rnd) or IsNaN(rnd) then
890 else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
893 result128 <- si128_CONVERT_FROM_BFP(rnd)
894 result <- result128[64:127] & js_mask
897 case(0): # Signed 32-bit
898 result <- EXTS64(result[32:63])
899 result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
900 case(1): # Unsigned 32-bit
901 result <- EXTZ64(result[32:63])
902 result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
903 case(2): # Signed 64-bit
904 result_bfp <- bfp_CONVERT_FROM_SI64(result)
905 default: # Unsigned 64-bit
906 result_bfp <- bfp_CONVERT_FROM_UI64(result)
908 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
909 if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
910 if xx_flag = 1 then SetFX(FPSCR.XX)
912 vx_flag <- vxsnan_flag | vxcvi_flag
913 vex_flag <- FPSCR.VE & vx_flag
917 FPSCR.FPRF <- undefined
920 if IsNaN(src) or not bfp_COMPARE_EQ(src, result_bfp) then
921 overflow <- 1 # signals SO only when OE = 1
927 Convert from 32-bit float in FRB to a unsigned/signed 32/64-bit integer
928 in RT, with the conversion overflow/rounding semantics following the
929 chosen `CVM` value, following the usual 32-bit float in 64-bit float
930 format. `FPSCR` is modified and exceptions are raised as usual.
932 These instructions have an Rc=1 mode which sets CR0 in the normal
933 way for any instructions producing a GPR result. Additionally, when OE=1,
934 if the numerical value of the FP number is not 100% accurately preserved
935 (due to truncation or saturation and including when the FP number was
936 NaN) then this is considered to be an Integer Overflow condition, and
937 CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
940 Special Registers altered:
943 XER SO, OV, OV32 (if OE=1)
944 FPCSR (TODO: which bits?)
948 | Assembly Alias | Full Instruction | Assembly Alias | Full Instruction |
949 |----------------------------|-----------------------------|----------------------------|-----------------------------|
950 | `fcvtstgw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 0` | `fcvtstgd RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 2` |
951 | `fcvtstgw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 0` | `fcvtstgd. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 2` |
952 | `fcvtstgwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 0` | `fcvtstgdo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 2` |
953 | `fcvtstgwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 0` | `fcvtstgdo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 2` |
954 | `fcvtstguw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 1` | `fcvtstgud RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 3` |
955 | `fcvtstguw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 1` | `fcvtstgud. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 3` |
956 | `fcvtstguwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 1` | `fcvtstgudo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 3` |
957 | `fcvtstguwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 1` | `fcvtstgudo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 3` |