1 # FPR-to-GPR and GPR-to-FPR
5 High-performance CPU/GPU software needs to often convert between integers
6 and floating-point, therefore fast conversion/data-movement instructions
7 are needed. Also given that initialisation of floats tends to take up
8 considerable space (even to just load 0.0) the inclusion of float immediate
9 is up for consideration (BF16 as immediates)
11 Libre-SOC will be compliant with the
12 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,
13 and with its focus on modern 3D GPU hybrid workloads represents an
14 important new potential use-case for OpenPOWER.
15 With VMX/VSX not available in the SFFS Compliancy Level, the
16 existing non-VSX conversion/data-movement instructions require load/store
17 instructions (slow and expensive) to transfer data between the FPRs and
18 the GPRs. Also, because SimpleV needs efficient scalar instructions in
19 order to generate efficient vector instructions, adding new instructions
20 for data-transfer/conversion between FPRs and GPRs seems necessary.
22 In addition, the vast majority of GPR <-> FPR data-transfers are as part
23 of a FP <-> Integer conversion sequence, therefore reducing the number
24 of instructions required to the minimum seems necessary.
26 Therefore, we are proposing adding:
28 * FPR load-immediate using `BF16` as the constant
29 * FPR <-> GPR data-transfer instructions that just copy bits without conversion
30 * FPR <-> GPR combined data-transfer/conversion instructions that do
31 Integer <-> FP conversions
33 If we're adding new Integer <-> FP conversion instructions, we may
34 as well take this opportunity to modernise the instructions and make them
35 well suited for common/important conversion sequences:
37 * standard Integer -> FP conversion
38 - rounding mode read from FPSCR
39 * standard OpenPower FP -> Integer conversion -- saturation with NaN
40 converted to minimum valid integer
41 - Matches x86's conversion semantics
42 - Has instructions for both:
43 * rounding mode read from FPSCR
44 * rounding mode is always truncate
45 * Rust FP -> Integer conversion -- saturation with NaN converted to 0
47 Semantics required by all of:
49 * Rust's FP -> Integer conversion using the
50 [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
52 [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
54 [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and
55 [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics
56 * SPIR-V's OpenCL dialect's
57 [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and
58 [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)
59 instructions when decorated with
60 [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).
61 * JavaScript FP -> Integer conversion -- modular with Inf/NaN converted to 0
63 Semantics required by JavaScript
65 TODO: review and investigate other language semantics
69 * <https://bugs.libre-soc.org/show_bug.cgi?id=650>
70 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c71>
71 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c74>
72 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c76>
74 # Proposed New Scalar Instructions
76 All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR.
78 This can be overridden by SimpleV, which sets the following
79 operation "reinterpretation" rules:
81 * any operation whose assembler mnemonic does not end in "s"
82 (being defined in v3.0B as a "double" operation) is
83 instead an operation at the overridden elwidth for the
85 * any operation nominally defined as a "single" FP operation
86 is redefined to be **half the elwidth** rather than
91 * `sv.fmvtg/sw=32 RT.v, FRA.v` is defined as treating FRA
92 as a vector of *FP32* source operands each *32* bits wide
93 which are to be placed into *64* bit integer destination elements.
94 * `sv.fmvfgs/dw=32 FRT.v, RA.v` is defined as taking the bottom
95 32 bits of each RA integer source, then performing a **32 bit**
96 FP32 to **FP16** conversion and storing the result in the
97 **32 bits** of an FRT destination element.
99 "Single" is therefore redefined in SVP64 to be "half elwidth"
100 rather than Double width hardcoded to 64 and Single width
101 hardcoded to 32. This allows a full range of conversions
102 between FP64, FP32, FP16 and BF16.
109 move a 64-bit float from a FPR to a GPR, just copying bits directly.
110 Rc=1 tests RT and sets CR0
115 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the
116 64-bit float in `FRA` to a 32-bit float, then writes the 32-bit float to
118 Rc=1 tests RT and sets CR0
124 move a 64-bit float from a GPR to a FPR, just copying bits.
128 move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
129 32-bit float in `RA` to a 64-bit float, then writes the 64-bit float to
134 ### Float load immediate (kinda a variant of `fmvfg`)
138 Reinterprets `FI << 16` as a 32-bit float, which is then converted to a
139 64-bit float and written to `FRT`. This is equivalent to reinterpreting
140 `FI` as a `BF16` and converting to 64-bit float.
146 fmvis f4, 0 # writes +0.0 to f4
147 # loading handy constants
148 fmvis f4, 0x8000 # writes -0.0 to f4
149 fmvis f4, 0x3F80 # writes +1.0 to f4
150 fmvis f4, 0xBF80 # writes -1.0 to f4
151 fmvis f4, 0xBFC0 # writes -1.5 to f4
152 fmvis f4, 0x7FC0 # writes +qNaN to f4
153 fmvis f4, 0x7F80 # writes +Infinity to f4
154 fmvis f4, 0xFF80 # writes -Infinity to f4
155 fmvis f4, 0x3FFF # writes +1.9921875 to f4
157 # clearing 128 FPRs with 2 SVP64 instructions
158 # by issuing 32 vec4 (subvector length 4) ops
160 sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
162 Important: If the float load immediate instruction(s) are left out,
163 change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
164 to instead write `+0.0` if `RA` is register `0`, at least
165 allowing clearing FPRs.
167 | 0-5 | 6-10 | 11-25 | 26-30 | 31 |
168 |--------|------|-------|-------|-----|
169 | Major | FRT | FI | XO | FI0 |
171 The above fits reasonably well with Minor 19 and follows the
172 pattern shown by `addpcis`, which uses an entire column of Minor 19
173 XO. 15 bits of FI fit into bits 11 to 25,
174 the top bit FI0 (MSB0 numbered 0) makes 16.
177 fp32 = bf16 || [0]*16
178 FRT = Single_to_Double(fp32)
180 ## FPR to GPR conversions
182 <div id="fpr-to-gpr-conversion-mode"></div>
186 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 |
187 |--------|------|--------|-------|-------|----|
188 | Major | RT | //Mode | FRA | XO | Rc |
189 | Major | FRT | //Mode | RA | XO | Rc |
193 | Mode | `rounding_mode` | Semantics |
194 |------|-----------------|----------------------------------|
195 | 000 | from `FPSCR` | [OpenPower semantics] |
196 | 001 | Truncate | [OpenPower semantics] |
197 | 010 | from `FPSCR` | [Rust semantics] |
198 | 011 | Truncate | [Rust semantics] |
199 | 100 | from `FPSCR` | [JavaScript semantics] |
200 | 101 | Truncate | [JavaScript semantics] |
201 | rest | -- | illegal instruction trap for now |
203 [OpenPower semantics]: #fp-to-int-openpower-conversion-semantics
204 [Rust semantics]: #fp-to-int-rust-conversion-semantics
205 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics
207 `fcvttgw RT, FRA, Mode`
209 Convert from 64-bit float to 32-bit signed integer, writing the result
210 to the GPR `RT`. Converts using [mode `Mode`]
212 `fcvttguw RT, FRA, Mode`
214 Convert from 64-bit float to 32-bit unsigned integer, writing the result
215 to the GPR `RT`. Converts using [mode `Mode`]
217 `fcvttgd RT, FRA, Mode`
219 Convert from 64-bit float to 64-bit signed integer, writing the result
220 to the GPR `RT`. Converts using [mode `Mode`]
222 `fcvttgud RT, FRA, Mode`
224 Convert from 64-bit float to 64-bit unsigned integer, writing the result
225 to the GPR `RT`. Converts using [mode `Mode`]
227 `fcvtstgw RT, FRA, Mode`
229 Convert from 32-bit float to 32-bit signed integer, writing the result
230 to the GPR `RT`. Converts using [mode `Mode`]
232 `fcvtstguw RT, FRA, Mode`
234 Convert from 32-bit float to 32-bit unsigned integer, writing the result
235 to the GPR `RT`. Converts using [mode `Mode`]
237 `fcvtstgd RT, FRA, Mode`
239 Convert from 32-bit float to 64-bit signed integer, writing the result
240 to the GPR `RT`. Converts using [mode `Mode`]
242 `fcvtstgud RT, FRA, Mode`
244 Convert from 32-bit float to 64-bit unsigned integer, writing the result
245 to the GPR `RT`. Converts using [mode `Mode`]
247 [mode `Mode`]: #fpr-to-gpr-conversion-mode
249 ## GPR to FPR conversions
251 All of the following GPR to FPR conversions use the rounding mode from `FPSCR`.
255 Convert from 32-bit signed integer in the GPR `RA` to 64-bit float in `FRT`.
259 Convert from 32-bit signed integer in the GPR `RA` to 32-bit float in `FRT`.
263 Convert from 32-bit unsigned integer in the GPR `RA` to 64-bit float in `FRT`.
267 Convert from 32-bit unsigned integer in the GPR `RA` to 32-bit float in `FRT`.
271 Convert from 64-bit signed integer in the GPR `RA` to 64-bit float in `FRT`.
275 Convert from 64-bit signed integer in the GPR `RA` to 32-bit float in `FRT`.
279 Convert from 64-bit unsigned integer in the GPR `RA` to 64-bit float in `FRT`.
283 Convert from 64-bit unsigned integer in the GPR `RA` to 32-bit float in `FRT`.
285 # FP to Integer Conversion Pseudo-code
289 | term | result type | definition |
290 |---------------------------|-------------|----------------------------------------------------------------------------------------------------|
291 | `fp` | -- | `f32` or `f64` (or other types from SimpleV) |
292 | `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) |
293 | `uint` | -- | the unsigned integer of the same bit-width as `int` |
294 | `int::BITS` | `int` | the bit-width of `int` |
295 | `int::MIN_VALUE` | `int` | the minimum value `int` can store (`0` if unsigned, `-2^(int::BITS-1)` if signed) |
296 | `int::MAX_VALUE` | `int` | the maximum value `int` can store (`2^int::BITS - 1` if unsigned, `2^(int::BITS-1) - 1` if signed) |
297 | `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. |
298 | `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
300 <div id="fp-to-int-openpower-conversion-semantics"></div>
301 OpenPower conversion semantics (section A.2 page 999 (page 1023) of OpenPower ISA v3.1):
304 def fp_to_int_open_power<fp, int>(v: fp) -> int:
306 return int::MIN_VALUE
307 if v >= int::MAX_VALUE:
308 return int::MAX_VALUE
309 if v <= int::MIN_VALUE:
310 return int::MIN_VALUE
311 return (int)rint(v, rounding_mode)
314 <div id="fp-to-int-rust-conversion-semantics"></div>
315 Rust [conversion semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics) (with adjustment to add non-truncate rounding modes):
318 def fp_to_int_rust<fp, int>(v: fp) -> int:
321 if v >= int::MAX_VALUE:
322 return int::MAX_VALUE
323 if v <= int::MIN_VALUE:
324 return int::MIN_VALUE
325 return (int)rint(v, rounding_mode)
328 <div id="fp-to-int-javascript-conversion-semantics"></div>
329 JavaScript [conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32) (with adjustment to add non-truncate rounding modes):
332 def fp_to_int_java_script<fp, int>(v: fp) -> int:
333 if v is NaN or infinite:
335 v = rint(v, rounding_mode)
336 v = v mod int::VALUE_COUNT # 2^32 for i32, 2^64 for i64, result is non-negative