openpower/sv/int_fp_mv.mdwn

   1 # FPR-to-GPR and GPR-to-FPR
   2
   3 Introduction:
   4
   5 High-performance CPU/GPU software needs to often convert between integers
   6 and floating-point, therefore fast conversion/data-movement instructions
   7 are needed.  Also given that initialisation of floats tends to take up
   8 considerable space (even to just load 0.0) the inclusion of float immediate
   9 is up for consideration (BF16 as immediates)
  10
  11 Libre-SOC will be compliant with the
  12 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,
  13 and with its focus on modern 3D GPU hybrid workloads represents an
  14 important new potential use-case for OpenPOWER.
  15 With VMX/VSX not available in the SFFS Compliancy Level, the
  16 existing non-VSX conversion/data-movement instructions require load/store
  17 instructions (slow and expensive) to transfer data between the FPRs and
  18 the GPRs.  Also, because SimpleV needs efficient scalar instructions in
  19 order to generate efficient vector instructions, adding new instructions
  20 for data-transfer/conversion between FPRs and GPRs seems necessary.
  21
  22 In addition, the vast majority of GPR <-> FPR data-transfers are as part
  23 of a FP <-> Integer conversion sequence, therefore reducing the number
  24 of instructions required to the minimum seems necessary.
  25
  26 Therefore, we are proposing adding:
  27
  28 * FPR load-immediate using `BF16` as the constant
  29 * FPR <-> GPR data-transfer instructions that just copy bits without conversion
  30 * FPR <-> GPR combined data-transfer/conversion instructions that do
  31   Integer <-> FP conversions
  32
  33 If we're adding new Integer <-> FP conversion instructions, we may
  34 as well take this opportunity to modernise the instructions and make them
  35 well suited for common/important conversion sequences:
  36
  37 * standard Integer -> FP IEEE754 conversion (used by most languages and CPUs)
  38 * standard OpenPower FP -> Integer conversion (saturation with NaN
  39   converted to minimum valid integer)
  40 * Rust FP -> Integer conversion (saturation with NaN converted to 0)
  41 * JavaScript FP -> Integer conversion (modular with Inf/NaN converted to 0)
  42
  43 # A bit more research into integer - fp conversion
  44
  45 here is a paragraph which explains that there are different semantics
  46 for conversion, i don't know what the paragraph should say, but it needs
  47 to be here, to give some background.  it also acts as a lead-in to the
  48 sub-sections, introducing them and explaining why they are here, as
  49 justifications and background research as to why the ISA should support
  50 the feature being proposed.
  51
  52 *nothing* can be left to chance or guesswork.
  53
  54 ## standard Integer -> FP conversion
  55
  56 This conversion is outlined in the IEEE754 specification.  It is used
  57 by nearly all programming languages and CPUs.  In the case of OpenPOWER,
  58 the rounding mode is read from FPSCR
  59
  60 # standard OpenPower FP -> Integer conversion
  61
  62 TODO, explain this further, make this a complete sentence:
  63 "saturation with NaN converted to minimum valid integer"
  64
  65   - Matches x86's conversion semantics
  66   - Has instructions for both:
  67     * rounding mode read from FPSCR
  68     * rounding mode is always truncate
  69
  70 ## Rust FP -> Integer conversion
  71
  72 TODO, explain this further, the following is not a complete sentence,
  73 "saturation with NaN converted to 0"
  74
  75 Semantics required by all of:
  76 (what does this mean, what is "required"?
  77 what semantics are being referred to? the sentence needs completing:
  78 "For Rust integer conversion, the semantics required are shown by the
  79 following, all of which are supported in XYZ" something like that)
  80
  81 * Rust's FP -> Integer conversion using the
  82   [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
  83 * Java's
  84   [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
  85 * LLVM's
  86   [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and
  87   [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics
  88 * SPIR-V's OpenCL dialect's
  89   [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and
  90   [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)
  91   instructions when decorated with
  92   [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).
  93
  94 ## JavaScript FP -> Integer conversion
  95
  96 modular with Inf/NaN converted to 0
  97
  98 TODO, explain this further, it is not a sentence:
  99 "Semantics required by JavaScript"
 100
 101 ## Other languages
 102
 103 TODO: review and investigate other language semantics
 104
 105 # Links
 106
 107 * <https://bugs.libre-soc.org/show_bug.cgi?id=650>
 108 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c71>
 109 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c74>
 110 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c76>
 111
 112 # Proposed New Scalar Instructions
 113
 114 All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR.
 115
 116 This can be overridden by SimpleV, which sets the following
 117 operation "reinterpretation" rules:
 118
 119 * any operation whose assembler mnemonic does not end in "s"
 120   (being defined in v3.0B as a "double" operation) is
 121   instead an operation at the overridden elwidth for the
 122   relevant operand.
 123 * any operation nominally defined as a "single" FP operation
 124   is redefined to be **half the elwidth** rather than
 125   "half of 64 bit".
 126
 127 Examples:
 128
 129 * `sv.fmvtg/sw=32 RT.v, FRA.v` is defined as treating FRA
 130    as a vector of *FP32* source operands each *32* bits wide
 131    which are to be placed into *64* bit integer destination elements.
 132 * `sv.fmvfgs/dw=32 FRT.v, RA.v` is defined as taking the bottom
 133    32 bits of each RA integer source, then performing a **32 bit**
 134    FP32 to **FP16** conversion and storing the result in the
 135    **32 bits** of an FRT destination element.
 136
 137 "Single" is therefore redefined in SVP64 to be "half elwidth"
 138 rather than Double width hardcoded to 64 and Single width
 139 hardcoded to 32.  This allows a full range of conversions
 140 between FP64, FP32, FP16 and BF16.
 141
 142 ## FPR to GPR moves
 143
 144 * `fmvtg RT, FRA`
 145 * `fmvtg. RT, FRA`
 146
 147 move a 64-bit float from a FPR to a GPR, just copying bits directly.
 148 Rc=1 tests RT and sets CR0
 149
 150 * `fmvtgs RT, FRA`
 151 * `fmvtgs. RT, FRA`
 152
 153 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the
 154 64-bit float in `FRA` to a 32-bit float, then writes the 32-bit float to
 155 `RT`.
 156 Rc=1 tests RT and sets CR0
 157
 158 ## GPR to FPR moves
 159
 160 `fmvfg FRT, RA`
 161
 162 move a 64-bit float from a GPR to a FPR, just copying bits. No exceptions
 163 are raised, no flags are altered of any kind.
 164
 165 TODO: Rc=1 variants?
 166
 167 `fmvfgs FRT, RA`
 168
 169 move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
 170 32-bit float in `RA` to a 64-bit float, then writes the 64-bit float to
 171 `FRT`.
 172
 173 TODO: Rc=1 variants?
 174
 175 TODO: clear statement on evaluation as to whethrer exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the conversion part.  the semantics should really be the same as frsp)
 176
 177 v3.0C section 4.6.7.1 states:
 178
 179 FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.
 180
 181     Special Registers Altered:
 182       FPRF FR FI
 183       FX OX UX XX VXSNAN
 184       CR1 (if Rc=1)
 185
 186 ### Float load immediate (kinda a variant of `fmvfg`)
 187
 188 `fmvis FRT, FI`
 189
 190 Reinterprets `FI << 16` as a 32-bit float, which is then converted to a
 191 64-bit float and written to `FRT`.  This is equivalent to reinterpreting
 192 `FI` as a `BF16` and converting to 64-bit float.
 193
 194 Example:
 195
 196 ```
 197 # clearing a FPR
 198 fmvis f4, 0 # writes +0.0 to f4
 199 # loading handy constants
 200 fmvis f4, 0x8000 # writes -0.0 to f4
 201 fmvis f4, 0x3F80 # writes +1.0 to f4
 202 fmvis f4, 0xBF80 # writes -1.0 to f4
 203 fmvis f4, 0xBFC0 # writes -1.5 to f4
 204 fmvis f4, 0x7FC0 # writes +qNaN to f4
 205 fmvis f4, 0x7F80 # writes +Infinity to f4
 206 fmvis f4, 0xFF80 # writes -Infinity to f4
 207 fmvis f4, 0x3FFF # writes +1.9921875 to f4
 208
 209 # clearing 128 FPRs with 2 SVP64 instructions
 210 # by issuing 32 vec4 (subvector length 4) ops
 211 setvli VL=MVL=32
 212 sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
 213 ```
 214 Important: If the float load immediate instruction(s) are left out,
 215 change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
 216 to instead write `+0.0` if `RA` is register `0`, at least
 217 allowing clearing FPRs.
 218
 219 |  0-5   | 6-10 | 11-25 | 26-30 | 31  |
 220 |--------|------|-------|-------|-----|
 221 |  Major | FRT  | FI    | XO    | FI0 |
 222
 223 The above fits reasonably well with Minor 19 and follows the
 224 pattern shown by `addpcis`, which uses an entire column of Minor 19
 225 XO.  15 bits of FI fit into bits 11 to 25,
 226 the top bit FI0 (MSB0 numbered 0) makes 16.
 227
 228     bf16 = FI0 || FI
 229     fp32 = bf16 || [0]*16
 230     FRT = Single_to_Double(fp32)
 231
 232 ## FPR to GPR conversions
 233
 234 <div id="fpr-to-gpr-conversion-mode"></div>
 235
 236 X-Form:
 237
 238 |  0-5   | 6-10 | 11-15  | 16-25 | 26-30 | 31 |
 239 |--------|------|--------|-------|-------|----|
 240 |  Major | RT   | //Mode | FRA   | XO    | Rc |
 241 |  Major | FRT  | //Mode | RA    | XO    | Rc |
 242
 243 Mode values:
 244
 245 | Mode | `rounding_mode` | Semantics                        |
 246 |------|-----------------|----------------------------------|
 247 | 000  | from `FPSCR`    | [OpenPower semantics]            |
 248 | 001  | Truncate        | [OpenPower semantics]            |
 249 | 010  | from `FPSCR`    | [Rust semantics]                 |
 250 | 011  | Truncate        | [Rust semantics]                 |
 251 | 100  | from `FPSCR`    | [JavaScript semantics]           |
 252 | 101  | Truncate        | [JavaScript semantics]           |
 253 | rest | --              | illegal instruction trap for now |
 254
 255 [OpenPower semantics]: #fp-to-int-openpower-conversion-semantics
 256 [Rust semantics]: #fp-to-int-rust-conversion-semantics
 257 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics
 258
 259 `fcvttgw RT, FRA, Mode`
 260
 261 Convert from 64-bit float to 32-bit signed integer, writing the result
 262 to the GPR `RT`. Converts using [mode `Mode`]
 263
 264 `fcvttguw RT, FRA, Mode`
 265
 266 Convert from 64-bit float to 32-bit unsigned integer, writing the result
 267 to the GPR `RT`. Converts using [mode `Mode`]
 268
 269 `fcvttgd RT, FRA, Mode`
 270
 271 Convert from 64-bit float to 64-bit signed integer, writing the result
 272 to the GPR `RT`. Converts using [mode `Mode`]
 273
 274 `fcvttgud RT, FRA, Mode`
 275
 276 Convert from 64-bit float to 64-bit unsigned integer, writing the result
 277 to the GPR `RT`. Converts using [mode `Mode`]
 278
 279 `fcvtstgw RT, FRA, Mode`
 280
 281 Convert from 32-bit float to 32-bit signed integer, writing the result
 282 to the GPR `RT`. Converts using [mode `Mode`]
 283
 284 `fcvtstguw RT, FRA, Mode`
 285
 286 Convert from 32-bit float to 32-bit unsigned integer, writing the result
 287 to the GPR `RT`. Converts using [mode `Mode`]
 288
 289 `fcvtstgd RT, FRA, Mode`
 290
 291 Convert from 32-bit float to 64-bit signed integer, writing the result
 292 to the GPR `RT`. Converts using [mode `Mode`]
 293
 294 `fcvtstgud RT, FRA, Mode`
 295
 296 Convert from 32-bit float to 64-bit unsigned integer, writing the result
 297 to the GPR `RT`. Converts using [mode `Mode`]
 298
 299 [mode `Mode`]: #fpr-to-gpr-conversion-mode
 300
 301 ## GPR to FPR conversions
 302
 303 All of the following GPR to FPR conversions use the rounding mode from `FPSCR`.
 304
 305 `fcvtfgw FRT, RA`
 306
 307 Convert from 32-bit signed integer in the GPR `RA` to 64-bit float in `FRT`.
 308
 309 `fcvtfgws FRT, RA`
 310
 311 Convert from 32-bit signed integer in the GPR `RA` to 32-bit float in `FRT`.
 312
 313 `fcvtfguw FRT, RA`
 314
 315 Convert from 32-bit unsigned integer in the GPR `RA` to 64-bit float in `FRT`.
 316
 317 `fcvtfguws FRT, RA`
 318
 319 Convert from 32-bit unsigned integer in the GPR `RA` to 32-bit float in `FRT`.
 320
 321 `fcvtfgd FRT, RA`
 322
 323 Convert from 64-bit signed integer in the GPR `RA` to 64-bit float in `FRT`.
 324
 325 `fcvtfgds FRT, RA`
 326
 327 Convert from 64-bit signed integer in the GPR `RA` to 32-bit float in `FRT`.
 328
 329 `fcvtfgud FRT, RA`
 330
 331 Convert from 64-bit unsigned integer in the GPR `RA` to 64-bit float in `FRT`.
 332
 333 `fcvtfguds FRT, RA`
 334
 335 Convert from 64-bit unsigned integer in the GPR `RA` to 32-bit float in `FRT`.
 336
 337 # FP to Integer Conversion Pseudo-code
 338
 339 Key for pseudo-code:
 340
 341 | term                      | result type | definition                                                                                         |
 342 |---------------------------|-------------|----------------------------------------------------------------------------------------------------|
 343 | `fp`                      | --          | `f32` or `f64` (or other types from SimpleV)                                                       |
 344 | `int`                     | --          | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV)                                              |
 345 | `uint`                    | --          | the unsigned integer of the same bit-width as `int`                                                |
 346 | `int::BITS`               | `int`       | the bit-width of `int`                                                                             |
 347 | `int::MIN_VALUE`          | `int`       | the minimum value `int` can store (`0` if unsigned, `-2^(int::BITS-1)` if signed)                  |
 348 | `int::MAX_VALUE`          | `int`       | the maximum value `int` can store (`2^int::BITS - 1` if unsigned, `2^(int::BITS-1) - 1` if signed) |
 349 | `int::VALUE_COUNT`        | Integer     | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`.           |
 350 | `rint(fp, rounding_mode)` | `fp`        | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode`      |
 351
 352 <div id="fp-to-int-openpower-conversion-semantics"></div>
 353 OpenPower conversion semantics (section A.2 page 999 (page 1023) of OpenPower ISA v3.1):
 354
 355 ```
 356 def fp_to_int_open_power<fp, int>(v: fp) -> int:
 357     if v is NaN:
 358         return int::MIN_VALUE
 359     if v >= int::MAX_VALUE:
 360         return int::MAX_VALUE
 361     if v <= int::MIN_VALUE:
 362         return int::MIN_VALUE
 363     return (int)rint(v, rounding_mode)
 364 ```
 365
 366 <div id="fp-to-int-rust-conversion-semantics"></div>
 367 Rust [conversion semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics) (with adjustment to add non-truncate rounding modes):
 368
 369 ```
 370 def fp_to_int_rust<fp, int>(v: fp) -> int:
 371     if v is NaN:
 372         return 0
 373     if v >= int::MAX_VALUE:
 374         return int::MAX_VALUE
 375     if v <= int::MIN_VALUE:
 376         return int::MIN_VALUE
 377     return (int)rint(v, rounding_mode)
 378 ```
 379
 380 <div id="fp-to-int-javascript-conversion-semantics"></div>
 381 JavaScript [conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32) (with adjustment to add non-truncate rounding modes):
 382
 383 ```
 384 def fp_to_int_java_script<fp, int>(v: fp) -> int:
 385     if v is NaN or infinite:
 386         return 0
 387     v = rint(v, rounding_mode)
 388     v = v mod int::VALUE_COUNT  # 2^32 for i32, 2^64 for i64, result is non-negative
 389     bits = (uint)v
 390     return (int)bits
 391 ```
 392
 393 # Equivalent OpenPower ISA v3.0 Assembly Language for FP -> Integer Conversion Modes
 394
 395 Moved to [[int_fp_mv/appendix]]