openpower/sv/int_fp_mv.mdwn

   1 [[!tag standards]]
   2
   3 # FPR-to-GPR and GPR-to-FPR
   4
   5 TODO special constants instruction (e, tau/N, ln 2, sqrt 2, etc.) -- exclude any constants available through fmvis
   6
   7 **Draft Status** under development, for submission as an RFC
   8
   9 Links:
  10
  11 * <https://bugs.libre-soc.org/show_bug.cgi?id=650>
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c71>
  13 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c74>
  14 * <https://bugs.libre-soc.org/show_bug.cgi?id=230#c76>
  15 * <https://bugs.libre-soc.org/show_bug.cgi?id=887> fmvis
  16 * [[int_fp_mv/appendix]]
  17
  18 Trademarks:
  19
  20 * Rust is a Trademark of the Rust Foundation
  21 * Java and Javascript are Trademarks of Oracle
  22 * LLVM is a Trademark of the LLVM Foundation
  23 * SPIR-V is a Trademark of the Khronos Group
  24 * OpenCL is a Trademark of Apple, Inc.
  25
  26 Referring to these Trademarks within this document
  27 is by necessity, in order to put the semantics of each language
  28 into context, and is considered "fair use" under Trademark
  29 Law.
  30
  31 Introduction:
  32
  33 High-performance CPU/GPU software needs to often convert between integers
  34 and floating-point, therefore fast conversion/data-movement instructions
  35 are needed.  Also given that initialisation of floats tends to take up
  36 considerable space (even to just load 0.0) the inclusion of two compact
  37 format float immediate instructions is up for consideration using 16-bit
  38 immediates. BF16 is one of the formats: a second instruction allows a full
  39 accuracy FP32 to be constructed.
  40
  41 Libre-SOC will be compliant with the
  42 **Scalar Floating-Point Subset** (SFFS) i.e. is not implementing VMX/VSX,
  43 and with its focus on modern 3D GPU hybrid workloads represents an
  44 important new potential use-case for OpenPOWER.
  45
  46 Prior to the formation of the Compliancy Levels first introduced
  47 in v3.0C and v3.1
  48 the progressive historic development of the Scalar parts of the Power ISA assumed
  49 that VSX would always be there to complement it. However With VMX/VSX
  50 **not available** in the newly-introduced SFFS Compliancy Level, the
  51 existing non-VSX conversion/data-movement instructions require
  52 a Vector of load/store
  53 instructions (slow and expensive) to transfer data between the FPRs and
  54 the GPRs.  For a modern 3D GPU this kills any possibility of a
  55 competitive edge.
  56 Also, because SimpleV needs efficient scalar instructions in
  57 order to generate efficient vector instructions, adding new instructions
  58 for data-transfer/conversion between FPRs and GPRs multiplies the savings.
  59
  60 In addition, the vast majority of GPR <-> FPR data-transfers are as part
  61 of a FP <-> Integer conversion sequence, therefore reducing the number
  62 of instructions required is a priority.
  63
  64 Therefore, we are proposing adding:
  65
  66 * FPR load-immediate instructions, one equivalent to `BF16`, the
  67   other increasing accuracy to `FP32`
  68 * FPR <-> GPR data-transfer instructions that just copy bits without conversion
  69 * FPR <-> GPR combined data-transfer/conversion instructions that do
  70   Integer <-> FP conversions
  71
  72 If adding new Integer <-> FP conversion instructions,
  73 the opportunity may be taken to modernise the instructions and make them
  74 well-suited for common/important conversion sequences:
  75
  76 * **standard IEEE754** - used by most languages and CPUs
  77 * **standard OpenPOWER** - saturation with NaN
  78   converted to minimum valid integer
  79 * **Java** - saturation with NaN converted to 0
  80 * **JavaScript** - modulo wrapping with Inf/NaN converted to 0
  81
  82 The assembly listings in the [[int_fp_mv/appendix]] show how costly
  83 some of these language-specific conversions are: Javascript, the
  84 worst case, is 32 scalar instructions including seven branch instructions.
  85
  86 # Proposed New Scalar Instructions
  87
  88 All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR.  All integers however are sourced/stored in the *GPR*.
  89
  90 Integer operands and results being in the GPR is the key differentiator between the proposed instructions
  91 (the entire rationale) compared to existing Scalar Power ISA.
  92 In all existing Power ISA Scalar conversion instructions, all
  93 operands are FPRs, even if the format of the source or destination
  94 data is actually a scalar integer.
  95
  96 *(The existing Scalar instructions being FP-FP only is based on an assumption
  97 that VSX will be implemented, and VSX is not part of the SFFS Compliancy
  98 Level. An earlier version of the Power ISA used to have similar
  99 FPR<->GPR instructions to these:
 100 they were deprecated due to this incorrect assumption that VSX would
 101 always be present).*
 102
 103 Note that source and destination widths can be overridden by SimpleV
 104 SVP64, and that SVP64 also has Saturation Modes *in addition*
 105 to those independently described here. SVP64 Overrides and Saturation
 106 work on *both* Fixed *and* Floating Point operands and results.
 107  The interactions with SVP64
 108 are explained in the  [[int_fp_mv/appendix]]
 109
 110 # Float load immediate  <a name="fmvis"></a>
 111
 112 These are like a variant of `fmvfg` and `oris`, combined.
 113 Power ISA currently requires a large
 114 number of instructions to get Floating Point constants into registers.
 115 `fmvis` on its own is equivalent to BF16 to FP32/64 conversion,
 116 but if followed up by `fishmv` an additional 16 bits of accuracy in the
 117 mantissa may be achieved.
 118
 119 *IBM may consider it worthwhile to extend these two instructions to
 120 v3.1 Prefixed (`pfmvis` and `pfishmv`: 8RR, imm0 extended).
 121 If so it is recommended that
 122 `pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high
 123 missing exponent bits (numbered 8 to 10) and the lower additional
 124 29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.
 125 Strictly speaking the sequence `fmvis fishmv pfishmv` achieves the
 126 same effect in the same number of bytes as `pfmvis pfishmv`,
 127 making `pfmvis` redundant.*
 128
 129 Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv.
 130 As fishmv is specifically intended to work in conjunction with fmvis
 131 to provide additional accuracy, all bits other than those which
 132 would have been set by a prior fmvis instruction are deliberately ignored.
 133
 134 ## Load BF16 Immediate
 135
 136 `fmvis FRS, D`
 137
 138 Reinterprets `D << 16` as a 32-bit float, which is then converted to a
 139 64-bit float and written to `FRS`.  This is equivalent to reinterpreting
 140 `D` as a `BF16` and converting to 64-bit float.
 141 There is no need for an Rc=1 variant because this is an immediate loading
 142 instruction.
 143
 144 Example:
 145
 146 ```
 147 # clearing a FPR
 148 fmvis f4, 0 # writes +0.0 to f4
 149 # loading handy constants
 150 fmvis f4, 0x8000 # writes -0.0 to f4
 151 fmvis f4, 0x3F80 # writes +1.0 to f4
 152 fmvis f4, 0xBF80 # writes -1.0 to f4
 153 fmvis f4, 0xBFC0 # writes -1.5 to f4
 154 fmvis f4, 0x7FC0 # writes +qNaN to f4
 155 fmvis f4, 0x7F80 # writes +Infinity to f4
 156 fmvis f4, 0xFF80 # writes -Infinity to f4
 157 fmvis f4, 0x3FFF # writes +1.9921875 to f4
 158
 159 # clearing 128 FPRs with 2 SVP64 instructions
 160 # by issuing 32 vec4 (subvector length 4) ops
 161 setvli VL=MVL=32
 162 sv.fmvis/vec4 f0, 0 # writes +0.0 to f0-f127
 163 ```
 164 Important: If the float load immediate instruction(s) are left out,
 165 change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
 166 to instead write `+0.0` if `RA` is register `0`, at least
 167 allowing clearing FPRs.
 168
 169 `fmvis` fits with DX-Form:
 170
 171 |  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form    |
 172 |--------|------|-------|-------|-------|-----|---------|
 173 |  Major | FRS  | d1    | d0    | XO    | d2  | DX-Form |
 174
 175 Pseudocode:
 176
 177     bf16 = d0 || d1 || d2 # create BF16 immediate
 178     fp32 = bf16 || [0]*16 # convert BF16 to FP32
 179     FRS = DOUBLE(fp32)    # convert FP32 to FP64
 180
 181 Special registers altered:
 182
 183     None
 184
 185 ## Float Immediate Second-Half MV <a name="fishmv"></a>
 186
 187 `fishmv FRS, D`
 188
 189 DX-Form:
 190
 191 |  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form    |
 192 |--------|------|-------|-------|-------|-----|---------|
 193 |  Major | FRS  | d1    | d0    | XO    | d2  | DX-Form |
 194
 195 Strategically similar to how `oris` is used to construct
 196 32-bit Integers, an additional 16-bits of immediate is
 197 inserted into `FRS` to extend its accuracy to
 198 a full FP32 (stored as usual in FP64 Format within the FPR).
 199 If a prior `fmvis` instruction had been used to
 200 set the upper 16-bits of an FP32 value, `fishmv` contains the
 201 lower 16-bits.
 202
 203 The key difference between using `li` and `oris` to construct 32-bit
 204 GPR Immediates and `fishmv` is that the `fmvis` will have converted
 205 the `BF16` immediate to FP64 (Double) format.
 206 This is taken into consideration
 207 as can be seen in the pseudocode below.
 208
 209 Pseudocode:
 210
 211     fp32 <- SINGLE((FRS))            # convert to FP32
 212     fp32[16:31] <- d0 || d1 || d2    # replace LSB half
 213     FRS <- DOUBLE(fp32)              # convert back to FP64
 214
 215 Special registers altered:
 216
 217     None
 218
 219 **This instruction performs a Read-Modify-Write.** *FRS is read, the additional
 220 16 bit immediate inserted, and the result also written to FRS*
 221
 222 Example:
 223
 224 ```
 225 # these two combined instructions write 0x3f808000
 226 # into f4 as an FP32 to be converted to an FP64.
 227 # actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
 228 # first the upper bits, happens to be +1.0
 229 fmvis f4, 0x3F80 # writes +1.0 to f4
 230 # now write the lower 16 bits of an FP32
 231 fishmv f4, 0x8000 # writes +1.00390625 to f4
 232 ```
 233
 234 # Moves
 235
 236 These instructions perform a straight unaltered bit-level copy from one Register
 237 File to another.
 238
 239 # FPR to GPR moves
 240
 241 * `fmvtg RT, FRA`
 242 * `fmvtg. RT, FRA`
 243
 244 move a 64-bit float from a FPR to a GPR, just copying bits directly.
 245 As a direct bitcopy, no exceptions occur and no status flags are set.
 246
 247 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
 248 operations.
 249
 250 * `fmvtgs RT, FRA`
 251 * `fmvtgs. RT, FRA`
 252
 253 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the
 254 64-bit float in `FRA` to a 32-bit float, using the same method as `stfs`,
 255 then writes the 32-bit float to `RT`, setting the high 32-bits to zeros.
 256 Effectively, `fmvtgs` is a macro-fusion of `stfs` and `lwz` and therefore
 257 does not behave like `frsp` and does not set any fp exception flags.
 258
 259 Since RT is a GPR, Rc=1 follows standard *integer* behaviour, i.e.
 260 tests RT and sets CR0.
 261
 262 # GPR to FPR moves
 263
 264 `fmvfg FRT, RA`
 265
 266 move a 64-bit float from a GPR to a FPR, just copying bits. No exceptions
 267 are raised, no flags are altered of any kind.
 268
 269 Rc=1 tests FRT and sets CR1
 270
 271 `fmvfgs FRT, RA`
 272
 273 move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
 274 32-bit float in `RA` to a 64-bit float, using the same method as `lfs`,
 275 then writes the 64-bit float to `FRT`. Effectively, `fmvfgs` is a
 276 macro-fusion of `stw` and `lfs` and therefore no fp exception flags are set.
 277
 278 Rc=1 tests FRT and sets CR1, following usual fp Rc=1 semantics.
 279
 280 # Conversions
 281
 282 Unlike the move instructions
 283 these instructions perform conversions between Integer and
 284 Floating Point. Truncation can therefore occur, as well
 285 as exceptions.
 286
 287 Mode values:
 288
 289 | Mode | `rounding_mode` | Semantics                        |
 290 |------|-----------------|----------------------------------|
 291 | 000  | from `FPSCR`    | [OpenPower semantics]            |
 292 | 001  | Truncate        | [OpenPower semantics]            |
 293 | 010  | from `FPSCR`    | [Java semantics]                 |
 294 | 011  | Truncate        | [Java semantics]                 |
 295 | 100  | from `FPSCR`    | [JavaScript semantics]           |
 296 | 101  | Truncate        | [JavaScript semantics]           |
 297 | rest | --              | illegal instruction trap for now |
 298
 299 [OpenPower semantics]: #fp-to-int-openpower-conversion-semantics
 300 [Java semantics]: #fp-to-int-java-conversion-semantics
 301 [JavaScript semantics]: #fp-to-int-javascript-conversion-semantics
 302
 303 ## GPR to FPR conversions
 304
 305 **Format**
 306
 307 |  0-5   | 6-10 | 11-15  | 16-25 | 26-30 | 31 | Form |
 308 |--------|------|--------|-------|-------|----|------|
 309 |  Major | FRT  | //Mode | RA    | XO    | Rc |X-Form|
 310
 311 All of the following GPR to FPR conversions use the rounding mode from `FPSCR`.
 312
 313 * `fcvtfgw FRT, RA`
 314   Convert from 32-bit signed integer in the GPR `RA` to 64-bit float in
 315   `FRT`.
 316 * `fcvtfgws FRT, RA`
 317   Convert from 32-bit signed integer in the GPR `RA` to 32-bit float in
 318   `FRT`.
 319 * `fcvtfguw FRT, RA`
 320   Convert from 32-bit unsigned integer in the GPR `RA` to 64-bit float in
 321   `FRT`.
 322 * `fcvtfguws FRT, RA`
 323   Convert from 32-bit unsigned integer in the GPR `RA` to 32-bit float in
 324   `FRT`.
 325 * `fcvtfgd FRT, RA`
 326   Convert from 64-bit signed integer in the GPR `RA` to 64-bit float in
 327   `FRT`.
 328 * `fcvtfgds FRT, RA`
 329   Convert from 64-bit signed integer in the GPR `RA` to 32-bit float in
 330   `FRT`.
 331 * `fcvtfgud FRT, RA`
 332   Convert from 64-bit unsigned integer in the GPR `RA` to 64-bit float in
 333   `FRT`.
 334 * `fcvtfguds FRT, RA`
 335   Convert from 64-bit unsigned integer in the GPR `RA` to 32-bit float in
 336   `FRT`.
 337
 338 ## FPR to GPR (Integer) conversions
 339
 340 <div id="fpr-to-gpr-conversion-mode"></div>
 341
 342 Different programming languages turn out to have completely different
 343 semantics for FP to Integer conversion.  Below is an overview
 344 of the different variants, listing the languages and hardware that
 345 implements each variant.
 346
 347 **Standard IEEE754 conversion**
 348
 349 This conversion is outlined in the IEEE754 specification.  It is used
 350 by nearly all programming languages and CPUs.  In the case of OpenPOWER,
 351 the rounding mode is read from FPSCR
 352
 353 **Standard OpenPower conversion**
 354
 355 This conversion, instead of exact IEEE754 Compliance, performs
 356 "saturation with NaN converted to minimum valid integer". This
 357 is also exactly the same as the x86 ISA conversion semantics.
 358 OpenPOWER however has instructions for both:
 359
 360 * rounding mode read from FPSCR
 361 * rounding mode always set to truncate
 362
 363 **Java conversion**
 364
 365 For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by Java's semantics (and Rust's `as` operator) will be referred to as
 366 [Java conversion semantics](#fp-to-int-java-conversion-semantics).
 367
 368 Those same semantics are used in some way by all of the following languages (not necessarily for the default conversion method):
 369
 370 * Java's
 371   [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
 372 * Rust's FP -> Integer conversion using the
 373   [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
 374 * LLVM's
 375   [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and
 376   [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics
 377 * SPIR-V's OpenCL dialect's
 378   [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and
 379   [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)
 380   instructions when decorated with
 381   [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).
 382 * WebAssembly has also introduced
 383  [trunc_sat_u](ttps://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-u) and
 384  [trunc_sat_s](https://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-s)
 385
 386 **JavaScript conversion**
 387
 388 For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by JavaScripts's `ToInt32` abstract operation will be referred to as [JavaScript conversion semantics](#fp-to-int-javascript-conversion-semantics).
 389
 390 This instruction is present in ARM assembler as FJCVTZS
 391 <https://developer.arm.com/documentation/dui0801/g/hko1477562192868>
 392
 393 **Format**
 394
 395 |  0-5   | 6-10 | 11-15  | 16-25 | 26-30 | 31 | Form |
 396 |--------|------|--------|-------|-------|----|------|
 397 |  Major | RT   | //Mode | FRA   | XO    | Rc |X-Form|
 398
 399 **Rc=1 and OE=1**
 400
 401 All of these insructions have an Rc=1 mode which sets CR0
 402 in the normal way for any instructions producing a GPR result.
 403 Additionally, when OE=1, if the numerical value of the FP number
 404 is not 100% accurately preserved (due to truncation or saturation
 405 and including when the FP number was NaN) then this is considered
 406 to be an integer Overflow condition, and CR0.SO, XER.SO and XER.OV
 407 are all set as normal for any GPR instructions that overflow.
 408
 409 **Instructions**
 410
 411 * `fcvttgw RT, FRA, Mode`
 412   Convert from 64-bit float to 32-bit signed integer, writing the result
 413   to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiw` or `fctiwz`
 414 * `fcvttguw RT, FRA, Mode`
 415   Convert from 64-bit float to 32-bit unsigned integer, writing the result
 416   to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiwu` or `fctiwuz`
 417 * `fcvttgd RT, FRA, Mode`
 418   Convert from 64-bit float to 64-bit signed integer, writing the result
 419   to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctid` or `fctidz`
 420 * `fcvttgud RT, FRA, Mode`
 421   Convert from 64-bit float to 64-bit unsigned integer, writing the result
 422   to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctidu` or `fctiduz`
 423 * `fcvtstgw RT, FRA, Mode`
 424   Convert from 32-bit float to 32-bit signed integer, writing the result
 425   to the GPR `RT`. Converts using [mode `Mode`]
 426 * `fcvtstguw RT, FRA, Mode`
 427   Convert from 32-bit float to 32-bit unsigned integer, writing the result
 428   to the GPR `RT`. Converts using [mode `Mode`]
 429 * `fcvtstgd RT, FRA, Mode`
 430   Convert from 32-bit float to 64-bit signed integer, writing the result
 431   to the GPR `RT`. Converts using [mode `Mode`]
 432 * `fcvtstgud RT, FRA, Mode`
 433   Convert from 32-bit float to 64-bit unsigned integer, writing the result
 434   to the GPR `RT`. Converts using [mode `Mode`]
 435
 436 [mode `Mode`]: #fpr-to-gpr-conversion-mode
 437
 438 ## FP to Integer Conversion Pseudo-code
 439
 440 Key for pseudo-code:
 441
 442 | term                      | result type | definition                                                                                         |
 443 |---------------------------|-------------|----------------------------------------------------------------------------------------------------|
 444 | `fp`                      | --          | `f32` or `f64` (or other types from SimpleV)                                                       |
 445 | `int`                     | --          | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV)                                              |
 446 | `uint`                    | --          | the unsigned integer of the same bit-width as `int`                                                |
 447 | `int::BITS`               | `int`       | the bit-width of `int`                                                                             |
 448 | `uint::MIN_VALUE`         | `uint`      | the minimum value `uint` can store: `0`                   |
 449 | `uint::MAX_VALUE`          | `uint`       | the maximum value `uint` can store: `2^int::BITS - 1`  |
 450 | `int::MIN_VALUE`          | `int`       | the minimum value `int` can store : `-2^(int::BITS-1)`              |
 451 | `int::MAX_VALUE`          | `int`       | the maximum value `int` can store :  `2^(int::BITS-1) - 1`  |
 452 | `int::VALUE_COUNT`        | Integer     | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`.           |
 453 | `rint(fp, rounding_mode)` | `fp`        | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode`      |
 454
 455 <div id="fp-to-int-openpower-conversion-semantics"></div>
 456 OpenPower conversion semantics (section A.2 page 999 (page 1023) of OpenPower ISA v3.1):
 457
 458 ```
 459 def fp_to_int_open_power<fp, int>(v: fp) -> int:
 460     if v is NaN:
 461         return int::MIN_VALUE
 462     if v >= int::MAX_VALUE:
 463         return int::MAX_VALUE
 464     if v <= int::MIN_VALUE:
 465         return int::MIN_VALUE
 466     return (int)rint(v, rounding_mode)
 467 ```
 468
 469 <div id="fp-to-int-java-conversion-semantics"></div>
 470 [Java conversion semantics](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
 471 /
 472 [Rust semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
 473 (with adjustment to add non-truncate rounding modes):
 474
 475 ```
 476 def fp_to_int_java<fp, int>(v: fp) -> int:
 477     if v is NaN:
 478         return 0
 479     if v >= int::MAX_VALUE:
 480         return int::MAX_VALUE
 481     if v <= int::MIN_VALUE:
 482         return int::MIN_VALUE
 483     return (int)rint(v, rounding_mode)
 484 ```
 485
 486 <div id="fp-to-int-javascript-conversion-semantics"></div>
 487 Section 7.1 of the ECMAScript / JavaScript
 488 [conversion semantics](https://262.ecma-international.org/11.0/#sec-toint32) (with adjustment to add non-truncate rounding modes):
 489
 490 ```
 491 def fp_to_int_java_script<fp, int>(v: fp) -> int:
 492     if v is NaN or infinite:
 493         return 0
 494     v = rint(v, rounding_mode)  # assume no loss of precision in result
 495     v = v mod int::VALUE_COUNT  # 2^32 for i32, 2^64 for i64, result is non-negative
 496     bits = (uint)v
 497     return (int)bits
 498 ```
 499