openpower/sv/mv.swizzle.mdwn

   1 [[!tag standards]]
   2
   3 # mv.swizzle
   4
   5 Links
   6
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=139>
   8
   9 TODO: evaluate whether this will fit with [[mv.vec]]
  10
  11 the encoding embeds predication into the swizzle as well as constants 1/1.0 and 0/0.0
  12
  13 # Format
  14
  15 | 0.5 |6.10|11.15|16.20|21.....25|26.....30|31|  name        |
  16 |-----|----|-----|-----|---------|---------|--|--------------|
  17 | 19  | RT | RA  |     | XO[0:4] | XO[5:9] |Rc| XL-Form      |
  18 | 19  | RT | RA  |imm  | imm     | 01 M im |0 | mv.vec.swiz  |
  19 | 19  | RT | RA  |imm  | imm     | 01 M im |1 | fmv.vec.swiz |
  20 | 19  | RT | RA  |imm  | imm     | 11 0 im |0 | mv.swiz      |
  21 | 19  | RT | RA  |imm  | imm     | 11 0 im |1 | fmv.swiz     |
  22
  23 this gives a 12 bit immediate across bits 16 to 25 and 29-30.
  24
  25 * 3 bits X
  26 * 3 bits Y
  27 * 3 bits Z
  28 * 3 bits W
  29
  30 except that the options are:
  31
  32 * 0b0NN index 0 thru 3 to place subelement in pos XYZW
  33 * 0b110 to indicate "skip".  this is equivalent to predicate masking
  34 * 0b100 to indicate "constant 0"
  35 * 0b101 to indicate "constant 1" (or 1.0)
  36 * 0b111 is not needed.
  37
  38 Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 comes out to 2,400 which is larger than 11 bits.
  39
  40 Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate.
  41
  42 Mode M is described in [[mv.vec]] and allows for merge and split of vectors.