openpower/sv/mv.vec.mdwn

   1 [[!tag standards]]
   2
   3 # Vector mv operations
   4
   5 In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more.  [[svp64]] provides the Vector Context to also add saturation as well as predication.
   6
   7 See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
   8
   9 Note that some of these may be covered by [[remap]] which is described in [[sv/propagation]]
  10
  11 # move to/from vec2/3/4
  12
  13 Basic idea: mv operations where either the src or dest is specifically marked as having SUBVL apply to it, but, crucially, the *other* argument does *not*. Note that this is highly unusual in SimpleV, which normally only allows SUBVL to be applied uniformly across all dest and all src.
  14
  15      mv.srcvec  r3, r4.vec2
  16      mv.destvec r2.vec4, r5
  17
  18 TODO: evaluate whether this will fit with [[mv.swizzle]] involved as well
  19 (yes it probably will)
  20
  21 * M=0 is mv.srcvec
  22 * M=1 is mv.destvec
  23
  24 mv.srcvec (leaving out elwidths and chop):
  25
  26     for i in range(VL):
  27         regs[rd+i] = regs[rs+i*SUBVL]
  28
  29 mv.destvec (leaving out elwidths and chop):
  30
  31     for i in range(VL):
  32         regs[rd+i*SUBVL] = regs[rs+i]
  33
  34 Note that these mv operations only become significant when elwidth is set on the vector to a small value.  SUBVL=4, src elwidth=8, dest elwidth=32 for example.
  35
  36 intended to cover:
  37
  38     rd = (rs >> 0 * 8) & (2^8 - 1)
  39     rd+1 = (rs >> 1 * 8) & (2^8 - 1)
  40     rd+2 = (rs >> 2 * 8) & (2^8 - 1)
  41     rd+3 = (rs >> 3 * 8) & (2^8 - 1)
  42
  43 and variants involving vec3 into 32 bit (4th byte set to zero).
  44 TODO: include this pseudocode which shows how the vecN can do that.
  45 in this example RA elwidth=32 and RB elwidth=8, RB is a vec4.
  46
  47     for i in range(VL):
  48          if predicate_bit_not_set(i) continue
  49          uint8_t *start_point = (uint8_t*)(int_regfile[RA].i[i])
  50          for j in range(SUBVL): # vec4
  51               start_point[j] = some_op(int_regfile[RB].b[i*SUBVL + j])
  52
  53 ## Twin Predication, saturation, swizzle, and elwidth overrides
  54
  55 Note that mv is a twin-predicated operation, and is swizzlable.  This implies that from the vec2, vec3 or vec4, 1 to 8 bytes may be selected and re-ordered (XYZW), mixed with 0 and 1 constants, skipped by way of twin predicate pack and unpack, and a huge amount besides.
  56
  57 Also saturation can be applied to individual elements, including the elements within a vec2/3/4.
  58
  59 # mv.zip and unzip
  60
  61 | 0.5 |6.10|11.15|16..20|21..25|26.....30|31|  name        |
  62 |-----|----|-----|------|------|---------|--|--------------|
  63 | 19  | RT | RC  | RB/0 | RA/0 | XO[5:9] |Rc| mv.zip       |
  64 | 19  | RT | RC  | RS/0 | RA/0 | XO[5:9] |Rc| mv.unzip     |
  65
  66 these are specialist operations that zip or unzip to/from multiple regs to/from one vector including vec2/3/4. when SUBVL!=1 the vec2/3/4 is the contiguous unit that is copied (as if one register).  different elwidths result in zero-extension or truncation except if saturation is enabled, where signed/unsigned may be applied as usual.
  67
  68 mv.zip, RA=0, RB=0
  69
  70     for i in range(VL):
  71         regs[rt+i] = regs[rc+i]
  72
  73 mv.zip, RA=0, RB!=0
  74
  75     for i in range(VL):
  76         regs[rt+i*2  ] = regs[rb+i]
  77         regs[rt+i*2+1] = regs[rc+i]
  78
  79 mv.zip, RA!=0, RB!=0
  80
  81     for i in range(VL):
  82         regs[rt+i*3  ] = regs[rb+i]
  83         regs[rt+i*3+1] = regs[rc+i]
  84         regs[rt+i*3+2] = regs[ra+i]