openpower/sv/mv.vec.mdwn

   1 [[!tag standards]]
   2
   3 # Vector Pack/Unpack operations
   4
   5 In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. Additional pixel pack/unpack instructions
   6 also exist.
   7
   8 In SVP64, Pack and Unpack are achieved *in the abstract* for application on *all*
   9 Vectorizeable instructions.
  10
  11 * See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
  12 * <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-June/004911.html>
  13
  14 The effect of Pack and unpack could be covered by [[sv/remap]] by using Matrix 2D layouts on either source or destination but is quite expensive to do so.  Additionally,
  15 with pressure on the Scalar 32-bit opcode space it is more appropriate to
  16 compromise by adding required capability in SVP64 as a high priority
  17 (part of the Management Instructions).  [[sv/mv.swizzle]] is sufficiently
  18 unusual to justify a base Scalar 32-bit instruction but pack/unpack is not.
  19 What, ultimately, was decided, was to make Pack/Unpack part of the
  20 `SVSTATE` [[sv/spr]].
  21
  22 # SVSTATE Pack/unpack Mode bits
  23
  24 Described in [[svp64/appendix]] the Pack/Unpack Modes allow selective
  25 Transposition of Sub-vector elements, on both source and destination.
  26 [[sv/mv.swizzle]] is unique in that the Subvector length may be different
  27 for source and destination.