3 # Vector Pack/Unpack operations
5 In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more. [[svp64]] provides the Vector Context to also add saturation as well as predication.
7 * See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
8 * <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-June/004911.html>
10 Pack and unpack may be covered by [[sv/remap]] by using Matrix 2D layouts on either source or destination but is quite expensive to do so. Additionally,
11 with pressure on the Scalar 32-bit opcode space it is more appropriate to
12 compromise by adding required capability in SVP64 on top of a
13 base pre-existing Scalar mv instruction. [[sv/mv.swizzle]] is sufficiently
14 unusual to justify a base Scalar 32-bit instruction but pack/unpack is not.
15 Both may benefit from a use of the `RM.EXTRA` field to provide an
16 additional mode, that may be applied to vec2/3/4.
18 # REMAP concept for pack/unpack
20 It may be possible to use one standard mv instruction to perform packing
21 and unpacking: Matrix allows for both reordering and offsets. At the very least a predicate mask potentially can
24 * If a single src-dest mv is used, then it potentially requires
25 two separate REMAP and two separate sv.mvs: remap-even, sv.mv,
27 * If adding twin-src and twin-dest that is a lot of instructions,
28 particularly if triple is added as well. FPR mv, GPR mv
29 * Unless twin or triple is added, how is it possible to determine
30 the extra register(s) to be merged (or split)?
32 How about instead relying on the implicit RS=MAXVL+RT trick and
33 extending that to RS=MAXVL+RA as a source? One spare bit in the
34 EXTRA RM area says whether the sv.mv is a pack (RS-as-src=RA+MAXVL)
35 or unpack (RS-as-dest=RT+MAXVL)
37 Alternatively, given that Matrix is up to 3 Dimensions, not even
38 be concerned about RS, just simply use one of those dimensions to
44 * RT set to YX, ydim=2, xdim=4
47 The indices match up as follows:
49 | RA | (0 1) (2 3) (4 5) (6 7) |
50 | RT | 0 2 4 8 1 3 5 7 |
52 This results in a 2-element "unpack"
57 * RT set to YX, ydim=3, xdim=3
60 The indices match up as follows:
62 | RA | 0 1 2 3 4 5 6 7 8 |
63 | RT | (0 3 6) (1 4 7) (2 5 8) |
65 This results in a 3-element "pack"
67 Both examples become particularly fun when Twin Predication is thrown
70 There exists room within the `svshape` instruction of [[sv/remap]]
71 to request some alternative Matrix mappings, and there is also
72 room within the reserved bits of `svremap` as well.
76 Also used on [[sv/mv.swizzle]]
78 `RM-2P-1S1D-PU` Mode, described in [[svp64/appendix]]
79 is applicable to all mv operations
80 (fmv etc) and to Indexed LD/ST.