openpower/sv/normal.mdwn

   1 [[!tag standards]]
   2
   3 # Normal SVP64 Modes, for Arithmetic and Logical Operations
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=574>
   6 * <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47>
   7 * [[svp64]]
   8
   9 Normal SVP64 Mode covers Arithmetic and Logical operations
  10 to provide suitable additional behaviour.  The Mode
  11 field is bits 19-23 of the [[svp64]] RM Field.
  12
  13 Table of contents:
  14
  15 [[!toc]]
  16
  17 # Mode
  18
  19 Mode is an augmentation of SV behaviour, providing additional
  20 functionality.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
  21
  22 [[sv/ldst]],
  23 [[sv/cr_ops]] and [[sv/branches]] are covered separately: the following
  24 Modes apply to Arithmetic and Logical SVP64 operations:
  25
  26 * **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
  27 * **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criteria.
  28   *VL is altered as a result*.
  29 * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping for both INT
  30 and FP.
  31 * **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see [[svp64/appendix]]
  32   note that there are comprehensive caveats when using this mode.
  33 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch conditional testing) and if the test fails it
  34 is as if the
  35 *destination* predicate bit was zero even before starting the operation.
  36 When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  See appendix for details.
  37
  38 Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
  39
  40 The Mode table for Arithmetic and Logical operations
  41  is laid out as follows:
  42
  43 | 0-1 |  2  |  3   4  |  description              |
  44 | --- | --- |---------|-------------------------- |
  45 | 00  |   0 |  dz  sz | normal mode                      |
  46 | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  47 | 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
  48 | 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  49 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
  50 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
  51 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
  52 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
  53 | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
  54
  55 Fields:
  56
  57 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
  58 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
  59 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
  60 than the normal 0..VL-1
  61 * **SVM** sets "subvector" reduce mode
  62 * **N** sets signed/unsigned saturation.
  63 * **RC1** as if Rc=1, stores CRs *but not the result*
  64 * **VLi** VL inclusive: in fail-first mode, the truncation of
  65   VL *includes* the current element at the failure point rather
  66   than excludes it from the count.
  67
  68 For LD/ST Modes, see [[sv/ldst]].  For Condition Registers
  69 see [[sv/cr_ops]].
  70 For Branch modes, see [[sv/branches]].
  71
  72 # Rounding, clamp and saturate
  73
  74 See [[av_opcodes]] for relevant opcodes and use-cases.
  75
  76 To help ensure that audio quality is not compromised by overflow,
  77 "saturation" is provided, as well as a way to detect when saturation
  78 occurred if desired (Rc=1). When Rc=1 there will be a *vector* of CRs,
  79 one CR per element in the result (Note: this is different from VSX which
  80 has a single CR per block).
  81
  82 When N=0 the result is saturated to within the maximum range of an
  83 unsigned value.  For integer ops this will be 0 to 2^elwidth-1. Similar
  84 logic applies to FP operations, with the result being saturated to
  85 maximum rather than returning INF, and the minimum to +0.0
  86
  87 When N=1 the same occurs except that the result is saturated to the min
  88 or max of a signed result, and for FP to the min and max value rather
  89 than returning +/- INF.
  90
  91 When Rc=1, the CR "overflow" bit is set on the CR associated with the
  92 element, to indicate whether saturation occurred.  Note that due to
  93 the hugely detrimental effect it has on parallel processing, XER.SO is
  94 **ignored** completely and is **not** brought into play here.  The CR
  95 overflow bit is therefore simply set to zero if saturation did not occur,
  96 and to one if it did.
  97
  98 Note also that saturate on operations that  set OE=1 are
  99 `UNDEFINED` due to the conflicting use of the CR.so bit for storing if
 100 saturation occurred. Integer Operations that produce a Carry-Out (CA, CA32):
 101 these two bits will also be `UNDEFINED` if saturation is requested.
 102
 103 Post-analysis of the Vector of CRs to find out if any given element hit
 104 saturation may be done using a mapreduced CR op (cror), or by using the
 105 new crweird instruction, transferring the relevant CR bits to a scalar
 106 integer and testing it for nonzero.  see [[sv/cr_int_predication]]
 107
 108 Note that the operation takes place at the maximum bitwidth (max of
 109 src and dest elwidth) and that truncation occurs to the range of the
 110 dest elwidth.
 111
 112 # Reduce mode
 113
 114 Reduction in SVP64 is similar in essence to other Vector Processing
 115 ISAs, but leverages the underlying scalar Base v3.0B operations.
 116 Thus it is more a convention that the programmer may utilise to give
 117 the appearance and effect of a Horizontal Vector Reduction. Due
 118 to the unusual decoupling it is also possible to perform
 119 prefix-sum in certain circumstances. Details are in the [[svp64/appendix]]
 120
 121 # Fail-on-first
 122
 123 Data-dependent fail-on-first has two distinct variants: one for LD/ST,
 124 the other for arithmetic operations (actually, CR-driven).  Note in each
 125 case the assumption is that vector elements are required appear to be
 126 executed in sequential Program Order, element 0 being the first.
 127
 128
 129 * Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
 130   CR-creating operation produces a result (including cmp).  Similar to
 131   branch, an analysis of the CR is performed and if the test fails, the
 132   vector operation terminates and discards all element operations at and
 133   above the current one, and VL is truncated to either
 134   the *previous* element or the current one, depending on whether
 135   VLi (VL "inclusive") is set.
 136
 137 Thus the new VL comprises a contiguous vector of results,
 138 all of which pass the testing criteria (equal to zero, less than zero).
 139
 140 The CR-based data-driven fail-on-first is new and not found in ARM
 141 SVE or RVV. It is extremely useful for reducing instruction count,
 142 however requires speculative execution involving modifications of VL
 143 to get high performance implementations.  An additional mode (RC1=1)
 144 effectively turns what would otherwise be an arithmetic operation
 145 into a type of `cmp`.  The CR is stored (and the CR.eq bit tested
 146 against the `inv` field).
 147 If the CR.eq bit is equal to `inv` then the Vector is truncated and
 148 the loop ends.
 149 Note that when RC1=1 the result elements are never stored, only the CRs.
 150
 151 VLi is only available as an option when `Rc=0` (or for instructions
 152 which do not have Rc). When set, the current element is always
 153 also included in the count (the new length that VL will be set to).
 154 This may be useful in combination with "inv" to truncate the Vector
 155 to `exclude` elements that fail a test, or, in the case of implementations
 156 of strncpy, to include the terminating zero.
 157
 158 In CR-based data-driven fail-on-first there is only the option to select
 159 and test one bit of each CR (just as with branch BO).  For more complex
 160 tests this may be insufficient.  If that is the case, a vectorised crops
 161 (crand, cror) may be used, and ffirst applied to the crop instead of to
 162 the arithmetic vector.
 163
 164 One extremely important aspect of ffirst is:
 165
 166 * LDST ffirst may never set VL equal to zero.  This because on the first
 167   element an exception must be raised "as normal".
 168 * CR-based data-dependent ffirst on the other hand **can** set VL equal
 169   to zero. This is the only means in the entirety of SV that VL may be set
 170   to zero (with the exception of via the SV.STATE SPR).  When VL is set
 171   zero due to the first element failing the CR bit-test, all subsequent
 172   vectorised operations are effectively `nops` which is
 173   *precisely the desired and intended behaviour*.
 174
 175 CR-based data-dependent first on the other hand MUST not truncate VL
 176 arbitrarily to a length decided by the hardware: VL MUST only be
 177 truncated based explicitly on whether a test fails.
 178 This because it is a precise test on which algorithms
 179 will rely.
 180
 181 ## Data-dependent fail-first on CR operations (crand etc)
 182
 183 Operations that actually produce or alter CR Field as a result
 184 have their own SVP64 Mode, described
 185 in [[sv/cr_ops]]
 186
 187 # pred-result mode
 188
 189 This mode merges common CR testing with predication, saving on instruction
 190 count. Below is the pseudocode excluding predicate zeroing and elwidth
 191 overrides. Note that the pseudocode for [[sv/cr_ops]] is slightly different.
 192
 193     for i in range(VL):
 194         # predication test, skip all masked out elements.
 195         if predicate_masked_out(i):
 196              continue
 197         result = op(iregs[RA+i], iregs[RB+i])
 198         CRnew = analyse(result) # calculates eq/lt/gt
 199         # Rc=1 always stores the CR
 200         if Rc=1 or RC1:
 201             crregs[offs+i] = CRnew
 202         # now test CR, similar to branch
 203         if RC1 or CRnew[BO[0:1]] != BO[2]:
 204             continue # test failed: cancel store
 205         # result optionally stored but CR always is
 206         iregs[RT+i] = result
 207
 208 The reason for allowing the CR element to be stored is so that
 209 post-analysis of the CR Vector may be carried out.  For example:
 210 Saturation may have occurred (and been prevented from updating, by the
 211 test) but it is desirable to know *which* elements fail saturation.
 212
 213 Note that RC1 Mode basically turns all operations into `cmp`.  The
 214 calculation is performed but it is only the CR that is written. The
 215 element result is *always* discarded, never written (just like `cmp`).
 216
 217 Note that predication is still respected: predicate zeroing is slightly
 218 different: elements that fail the CR test *or* are masked out are zero'd.
 219