openpower/sv/po9_encoding/discussion.mdwn

   1 # alternative 32-64 encoding
   2
   3 ```
   4 | 0-5 | 6-28 29 |30-31| 32 |33-37| 38-60 | 61-63 | Description       |
   5 |-----|---------|-----|----|-----|-----------------------------------|
   6 | PO9 | xxx | 0 | 0 0 |  0  00000  xxxx    000   | SVP64:EXT900       |
   7 | PO9 | xxx | 0 | 0 0 | !zero      xxxx    !zero | 55-bit RESERVED    |
   8 | PO9 | xxx | 1 | 0 0 |            32-bit EXT900                      |
   9 | PO9 |   !ZERO | 0 0 |  1 | DWi                 | SS:EXT232-263      |
  10 | PO9 |   0000  | 0 0 |  1 | DWi                 | Scalar EXT232-263  |
  11 | PO9 |   nnnn  | 1 0 |  1 | DWi                 | SVP64:EXT232-263   |
  12 | PO9 |   0000  | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b|
  13 | PO9 |   !ZERO | 0 1 | Defined Word-instruction | SS:EXT000-063      |
  14 | PO9 |   nnnn  | 1 1 | Defined Word-instruction | SVP64:EXT000-063   |
  15 ```
  16
  17 Length detection:
  18
  19 ```
  20     if PO1                   return 64
  21     elif not PO9             return 32
  22     elif Word[31] = 1        return 64
  23     elif Word[29:30] = 0b10  return 32
  24     elif Word[29:30] = 0b00  return 64
  25     else                     return 32
  26 ```
  27
  28 Instruction allocation restrictions:
  29
  30 * setvl is Unvectorizable but needs more space later: use 55-bit
  31 * likewise svshape svindex and svshape2, all these need 32-bit
  32 * svstep *is* Vectorizable but needs to be encoded 32-bit in order
  33   to reduce loop-size
  34 * space for 32-bit instructions is needed: some instructions
  35   just make no sense if done as 64-bit because they **replace**
  36   two 32-bit instructions.
  37 * but those types of space-saving instructions
  38   **also need to be Vectorizable*