openpower/sv/po9_encoding/discussion.mdwn

   1 # alternative 32-64 encoding
   2
   3 ```
   4 |0-5| 6-27 28 29|30-31| 32 |33-37   | 38-59 | 60-63 | Description       |
   5 |---|-----|-----|-----|----|--------|-----------------------------------|
   6 |PO9| rm0 | 0 0 | 0 0 |  0   000 rm1 xxxx    0000  | SVP64:EXT900       |
   7 |PO9| rm0 | 0 0 | 0 0 |  1   000 rm1 xxxx    0000  | SSingle:EXT900     |
   8 |PO9| xxx | x 0 | 0 0 |   !zero      xxxx    !zero | 55-bit RESERVED    |
   9 |PO9| xxx | x 0 | 0 0 |              32-bit EXT900 (Vectorizable)       |
  10 |PO9| xxx | 1 1 | 0 0 |              32-bit EXT901 (Unvectorizable)     |
  11 |PO9|   !ZERO   | 0 0 |  1 | DWi                   | SSingle:EXT232-263 |
  12 |PO9|   0000    | 0 0 |  1 | DWi                   | Scalar EXT232-263  |
  13 |PO9|   nnnn    | 1 0 |  1 | DWi                   | SVP64:EXT232-263   |
  14 |PO9|   0000    | 0 1 | Defined Word-instruction   | 32-bit Unvec in 64b|
  15 |PO9|   !ZERO   | 0 1 | Defined Word-instruction   | SSingle:EXT000-063 |
  16 |PO9|   nnnn    | 1 1 | Defined Word-instruction   | SVP64:EXT000-063   |
  17 ```
  18
  19 Fields:
  20
  21 * `SVRM <- rm0 || rm1`
  22
  23 Length detection:
  24
  25 ```
  26     if PO1                   return 64
  27     elif not PO9             return 32
  28     elif Word[31] = 1        return 64
  29     elif Word[29:30] = 0b10  return 32
  30     elif Word[29:30] = 0b00  return 64
  31     else                     return 32
  32 ```
  33
  34 Instruction allocation restrictions:
  35
  36 * setvl is Unvectorizable but needs more space later: use 55-bit
  37 * likewise svshape svindex and svshape2, all these need 32-bit
  38 * svstep *is* Vectorizable but needs to be encoded 32-bit in order
  39   to reduce loop-size
  40 * space for 32-bit instructions is needed: some instructions
  41   just make no sense if done as 64-bit because they **replace**
  42   two 32-bit instructions.
  43 * but those types of space-saving instructions
  44   **also need to be Vectorizable*