openpower/sv/po9_encoding/discussion.mdwn

   1 [[!toc]]
   2
   3 # alternative 32-64 encoding (1)
   4
   5 conflict to resolve: EXT90x and EXT232. they are indistinguishable.
   6
   7 ```
   8 |0-5| 6-27 28 29|30-31|32|33-35|36-37| 38-59 | 60-63 | Description      |
   9 |---|-----|-----|-----|--|-----|-----|-------|-------|------------------|
  10 |PO9| rm0 | 0 0 | 0 0 | 0  000   rm1 |  xxxx | 0000  | SVP64:EXT900     |
  11 |PO9| rm0 | 0 0 | 0 0 | 1  000   rm1 |  xxxx | 0000  | SSingle:EXT900   |
  12 |PO9| xxx | x 0 | 0 0 | x !zero0     |  xxxx | !zero1| 55-bit RESERVED  |
  13 |PO9| xxx | 0 1 | 0 0 |              32-bit EXT900 (Vectorizable)       |
  14 |PO9| xxx | 1 1 | 0 0 |              32-bit EXT901 (Unvectorizable)     |
  15 |PO9|   !ZERO   | 0 0 |  1 | DWi                   | SSingle:EXT232-263 |
  16 |PO9|   0000    | 0 0 |  1 | DWi                   | Scalar EXT232-263  |
  17 |PO9|   RM      | 1 0 |  1 | DWi                   | SVP64:EXT232-263   |
  18 |PO9|   0000    | 0 1 | Defined Word-instruction   | 32-bit Unvec in 64b|
  19 |PO9|   !ZERO   | 0 1 | Defined Word-instruction   | SSingle:EXT000-063 |
  20 |PO9|   RM      | 1 1 | Defined Word-instruction   | SVP64:EXT000-063   |
  21 ```
  22
  23 Fields:
  24
  25 * `RM`: 24-bit SVP64 prefix
  26 * `RM <- rm0 || rm1` split field
  27 * `!zero0 || !zero1` a split field that must not be zero
  28
  29 Length detection:
  30
  31 ```
  32     if PO1                   return 64
  33     elif not PO9             return 32
  34     elif Word[31] = 1        return 64
  35     elif Word[29:30] = 0b10  return 32
  36     elif Word[29:30] = 0b00  return 64
  37     else                     return 32
  38 ```
  39
  40 Instruction allocation restrictions:
  41
  42 * setvl is Unvectorizable but needs more space later: use 55-bit
  43 * likewise svshape svindex and svshape2, all these need 32-bit
  44 * svstep *is* Vectorizable but needs to be encoded 32-bit in order
  45   to reduce loop-size
  46 * space for 32-bit instructions is needed: some instructions
  47   just make no sense if done as 64-bit because they **replace**
  48   two 32-bit instructions.
  49 * but those types of space-saving instructions
  50   **also need to be Vectorizable*
  51
  52 # alternative 32-64 encoding (2)
  53
  54 requires reducing SVP64Single to 23 bits. luckily there are 2 spare
  55
  56 the complexity of attempting to fit 32-bit instructions into
  57 PO9 is very high. encoding (1) attempts to fit `setvl` etc. into
  58 32-bit but it is very tight.  the entire EXT900 area would be
  59 taken up by the SVP64 Management instructions, below, defeating
  60 the purpose of having it.
  61
  62 * `setvl` - Unvectorizable, EXT0xx, `RT RA CTR SVSTATE`, 6-bit XO (including Rc=1)
  63 * `psetvl` - Unvectorizable, EXT1xx, ditto
  64 * `svstep` - Vectorizable, either EXT900 (very precious) or EXT1xx (better), `RT, SVSTATE`, 6-bit XO (including Rc=1)
  65 * `svindex` - Unvectorizable, EXT0xx, `SVSTATE,SVSHAPE0-3`, 5-bit XO
  66 * `psvindex` - Unvectorizable, EXT1xx, ditto
  67 * `svstep(2)` - Unvectorizable, EXT0xx, `SVSTATE,SVSHAPE0-3`, 5-bit XO
  68 * `svstep(2)` - Unvectorizable, EXT1xx, ditto
  69
  70 ```
  71 |0-5| 6-28|29 30 31|32|33-36|37 | 38-60 | 61-63 | Description      |
  72 |---|-----|--------|--|-----|---|-------|-------|------------------|
  73 |PO9| rm0 | 1  0 0 | 0 0000  rm1|  xxxx | 000   | SVP64:EXT900     |
  74 |PO9|!ZERO| 1  0 0 | 0 1000  1  |  xxxx | 000   | SSingle:EXT900   |
  75 |PO9| xxx | 1  0 0 | 0 !zero0   |  xxxx | !zero1| 55-bit RESERVED  |
  76 |PO9| xxx | 0  0 0 |            32-bit EXT900                      |
  77 |PO9|!ZERO| 1  0 0 |  1 | DWi                 | SSingle:EXT232-263 |
  78 |PO9| 000 | 1  0 0 |  1 | DWi                 | Scalar EXT232-263  |
  79 |PO9|  nnnn  | 1 0 |  1 | DWi                 | SVP64:EXT232-263   |
  80 |PO9|  0000  | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b|
  81 |PO9|!ZERO   | 0 1 | Defined Word-instruction | SSingle:EXT000-063 |
  82 |PO9|  nnnn  | 1 1 | Defined Word-instruction | SVP64:EXT000-063   |
  83 ```
  84
  85 Length detection:
  86
  87 ```
  88     if PO1                   return 64
  89     elif not PO9             return 32
  90     elif Word[29:31] = 0b000 return 32
  91     else                     return 64
  92 ```
  93
  94 # alternative 32-64 encoding (3)
  95
  96 TODO
  97 aim of this idea is to attempt simplification of area identification
  98 and length.  the 55-bit area is eliminated and may only be reintroduced
  99 by sacrificing parts of EXT200-231, bear in mind that EXT209 is already
 100 unavailable (used by EXT900).
 101
 102
 103 ```
 104 |0-5| 6-29   |30 31|32|33-36|37 | 38-61 | 62-63 | Description      |
 105 |---|--------|-----|--|-----|---|-------|-------|------------------|
 106 |PO9| xxxx   | 0 0 | (next new instruction)     |  32-bit EXT900   |
 107 |PO9| 0000   | 1 0 | 0 1000  1  |  xxxx |  00   | RESERVED         |
 108 |PO9| !ZERO  | 1 0 | 0 1000  1  |  xxxx |  00   | SSingle:EXT900   |
 109 |PO9| nnnn   | 1 0 | 0 1000  1  |  xxxx |  01   | SVP64:EXT900     |
 110 |PO9| xxxx   | 1 0 | 0 1000  1  |  xxxx |  10   | RESERVED         |
 111 |PO9| xxxx   | 1 0 | 0 1000  1  |  xxxx |  11   | RESERVED         |
 112 |PO9| !ZERO  | 1 0 | 0 | !PO9   |     xxxx      | SSingle:EXT200-231 |
 113 |PO9|  0000  | 1 0 | 0 | !PO9   |     xxxx      | Scalar EXT200-231  |
 114 |PO9|  nnnn  | 1 0 | 1 | !PO9   |     xxxx      | SVP64:EXT200-231   |
 115 |PO9|  0000  | 0 1 | Defined Word-instruction | 32-bit Unvec in 64b|
 116 |PO9| !ZERO  | 0 1 | Defined Word-instruction | SSingle:EXT000-063 |
 117 |PO9|  nnnn  | 1 1 | Defined Word-instruction | SVP64:EXT000-063   |
 118 ```
 119
 120 Length detection:
 121
 122 ```
 123     if PO1                   return 64
 124     elif not PO9             return 32
 125     elif Word[30:31] = 0b00  return 32
 126     else                     return 64
 127 ```
 128
 129 EXT200-231:
 130
 131 ```
 132     if not PO9                return False
 133     if Word[30:31] != 0b00    return False
 134     if Word[33:37] != 0b10001 return False
 135 ```
 136