openpower/sv/po9_encoding.mdwn

   1 # Definitions
   2
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   4 [[po9_encoding/discussion]]
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   6
   7 **Add the following Definitions to Section 1.3.1 of Book I**
   8
   9 **Definition of Simple-V:**
  10
  11 In its simplest form, the Simple-V Loop/Vector concept is a Prefixing
  12 system (similar to the 8086 `REP` instruction and the Z80 `LDIR`)
  13 that both augments its
  14 following Defined Word-instruction (Suffix), and also may repeat that instruction
  15 with optional sequential register offsets from those given in the
  16 Suffix. Register numbers may also be extended (larger register files).
  17 More advanced features add predication, element-width overrides, and
  18 Vertical-First Mode.
  19
  20 **Definition of SVP64 Prefixing:**
  21
  22 SVP64 is a well-defined implementation of the Simple-V Loop/Vector concept,
  23 in a 32-bit Prefix format, that exploits the following instruction
  24 (the Defined Word-instruction) using it as a "template".  It requires 24 bits,
  25 some of which are common to all Suffixes, and some Mode bits are specific
  26 to the Defined Word-instruction class: Load/Store-Immediate, Load/Store-Indexed,
  27 Arithmetic/Logical, Condition Register operations, and Branch-Conditional.
  28 Anything not falling into those five categories is termed "Unvectorizable".
  29
  30 **Definition of Horizontal-First:**
  31
  32 Normal Cray-style Vectorization, designated Horizontal-First, performs
  33 element-level operations (often in parallel) before moving in the usual
  34 fashion to the next instruction. The term "Horizontal-First"
  35 stems from naturally visually listing program instructions vertically,
  36 and register file contents horizontally, whereupon it is clear that
  37 register-elements are prioritised.
  38
  39 **Definition of Vertical-First:**
  40
  41 Vertical-First executes
  42 *one element operation only* then moves on to the next instruction,
  43 whereupon if that is also an SVP64-Prefixed instruction the exact same
  44 element offset is used.  Element offsets are then explicitly advanced
  45 by calling a special instruction, `svstep`. The term "Vertical-First"
  46 stems from naturally visually listing program instructions vertically
  47 and register file contents horizontally, where moving to the next
  48 instruction is a clear priority.
  49
  50 **Definition of SVP64Single Prefixing:**
  51
  52 A 32-bit Prefix in front of a Defined Word-instruction that extends register
  53 numbers (allows larger register files), adds single-bit predication,
  54 element-width overrides, and optionally adds Saturation to Arithmetic
  55 instructions that normally would not have it.  *SVP64Single is in Draft only*
  56 and is yet to be defined.
  57
  58 **Definition of "Unvectorizable":**
  59
  60 Any operation that inherently makes no sense if repeated (through SVP64
  61 Prefixing) is termed "Unvectorizable".  Examples
  62 include `sc` or `sync` which have no registers. `mtmsr` is also classed
  63 as Unvectorizable because there is only one `MSR`. Also
  64 instructions that simply may not be Prefixed (EXT300-EXT363) are also
  65 deemed "Unvectorizable".
  66
  67 Unvectorizable instructions are required to be detected as such if Prefixed
  68 (either SVP64 or SVP64Single) and an Illegal Instruction Trap raised.
  69
  70 *Hardware Architectural Note: Given that a "pre-classification" Decode Phase
  71 is required (identifying whether the Suffix - Defined Word-instruction - is
  72 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), adding
  73 "Unvectorizable" detection to this phase is not unreasonable.*
  74
  75 # New Prefixed Instruction Encoding space
  76
  77 **Proposal: Add new Section 1.6.5 to Book I**
  78
  79 The following eight new `RESERVED` areas are defined within
  80 Primary Opcode 9 (EXT009)
  81
  82 |0-5| 6-29   |30 31|32-37   | 38-63 | Description      |
  83 |---|--------|-----|--------|-------|------------------|
  84 |PO9| xxxx   | x x | 010001 | xxxx  | RESERVED(1)      |
  85 |PO9| xxxx   | x x | 000001 | xxxx  | RESERVED(2)      |
  86 |PO9| !ZERO  | 1 1 |  !PO9  | nnnn  | SVP64Single:EXT200-263 |
  87 |PO9|  0000  | 1 1 |  !PO9  | nnnn  | Scalar EXT200-263  |
  88 |PO9|  SVRM  | 1 0 |  !PO9  | nnnn  | SVP64:EXT200-263   |
  89 |PO9|  0000  | 0 1 | DWd    | nnnn  | 32-bit EXT300-363  |
  90 |PO9| !ZERO  | 0 1 | DWd    | nnnn  | SVP64Single:EXT000-063 |
  91 |PO9|  SVRM  | 0 0 | DWd    | nnnn  | SVP64:EXT000-063   |
  92
  93 Key:
  94
  95 * **x** - a `RESERVED` encoding. Illegal Instruction Trap must be raised
  96 * **n** - a future specification-defined value (currently `RESERVED`)
  97 * **!PO9** - any 6-bit binary value except Primary Opcode 9 (0b010001)
  98 * **!ZERO** - a non-zero future specification-defined value (currently `RESERVED`)
  99 * **DWd** - a "Defined Word-instruction" - Book I Section 1.6 (Public v3.1 p11)
 100 * **SVRM** - a `RESERVED` encoding
 101 * **SVP64Single**: a future `RESERVED` Prefix encoding
 102 * **SVP64**: a future `RESERVED` Loop-Prefix encoding
 103 * **EXT200-263**: a `RESERVED` encoding for future Scalar instructions (Vectorizable)
 104 * **EXT300-363**: a `RESERVED` encoding for future Scalar instructions (Unvectorizable)
 105
 106 *Architectural Resource Allocation Note: Similar to ARM's `MOVPRFX`
 107 instruction and the original x86 REP instruction, despite "influence" over
 108 the Suffix, the Suffix is entirely independent of the Prefix.  Therefore
 109 **under no circumstances** must different Defined Word-instructions (different from
 110 the same **Un-Prefixed** Defined Word-instruction) be allocated within any `EXT{zNN}`
 111 prefixed or unprefixed space for a given value of `z` of 0, 2 or 3: the
 112 results would be catastrophic.  Even if Unvectorizable an instruction
 113 Defined Word-instruction space **must** have the exact same Instruction and exact same
 114 Instruction Encoding in all spaces being RESERVED (Illegal Instruction
 115 Trap if Unvectorizable) or not be allocated at all.  This is required
 116 as an inviolate hard rule governing Primary Opcode 9 that may not be
 117 revoked under any circumstances. A useful way to think of this is that
 118 the Prefix Encoding is, like the 8086 REP instruction, an independent
 119 32-bit Defined Word-instruction.*
 120
 121 Note a particular consequence of the application of the above paragraph:
 122 due to the fact that the Prefix Encodings are independent, **by
 123 definition** two new Sandbox areas "come into being" in an **inviolate**
 124 manner (i.e.  they may not be called anything else, nor may they
 125 be revoked rescinded removed or recalled), named `SVP64:EXT022` and
 126 `SVP64Single:EXT022`.  The **only way** that these two new areas may be
 127 revoked is if EXT022 itself is revoked.  **All and any** re-definitions
 128 modifications enhancements clarifications that apply to EXT022 **also
 129 apply to these two new areas** because due to the Prefixes being
 130 independent Defined Word-instructions the three areas are actually one and the same
 131 area, just as *all* Scalar Defined Word-instructions are.
 132
 133 Notes:
 134
 135 * **PO9**-PO1 Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
 136   thus inherently Unvectorizable as the complexity at the Decoder of recognising
 137   `{PO1-word}{PO9-word}{Defined-word-instruction}` becomes too great for High
 138   Performance Multi-Issue systems.
 139 * There is however no reason why PO9-PO1 (EXT901?) as an entirely new RESERVED
 140   64-bit Encoding
 141   should not be permitted as long as it is clearly marked as Unvectorizable.
 142 * PO1-**PO9** Prefixed-Prefixed (96-bit) instructions are also prohibited
 143   for the same reason: Multi-Issue Decode complexity is too great.
 144 * There is however no reason why PO1-PO9 (EXT109) as an entirely new RESERVED
 145   64-bit Encoding
 146   should not be permitted as long as it is clearly marked as Unvectorizable.
 147 * EXT100-163 instructions (PO1-Prefixed) are also prohibited from being
 148   double-PO1-prefixed (not twice prefixed)
 149 * Considerable care is needed both on Architectural Resource Allocation
 150   as well as instruction design itself. All new Scalar instructions automatically
 151   and inherently must be designed taking their Vectorizeable potential into
 152   consideration *including VSX* in future.
 153 * Once an instruction is allocated
 154   in an Unvectorizable area it can never be Vectorized without providing
 155   an entirely new Encoding.
 156
 157 [[!tag standards]]
 158
 159 --------
 160
 161 \newpage{}
 162