openpower/sv/po9_encoding.mdwn

   1 # New 64-bit Instruction Encoding spaces
   2
   3 The following seven new areas are defined within Primary Opcode 9 (EXT009)
   4 as a new 64-bit encoding space, alongside Primary Opcode 1
   5 (EXT1xx).
   6
   7 | 0-5 | 6 | 7 | 8-31  | 32| Description                        |
   8 |-----|---|---|-------|---|------------------------------------|
   9 | PO  | 0 | x | xxxx  | 0 | `RESERVED2` (57-bit) |
  10 | PO  | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
  11 | PO  | 0 | 0 | 0000  | 1 | Scalar EXT232-263               |
  12 | PO  | 0 | 1 | nnnn  | 1 | SVP64:EXT232-263     |
  13 | PO  | 1 | 0 | 0000  | x | `RESERVED1` (32-bit) |
  14 | PO  | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
  15 | PO  | 1 | 1 | nnnn  | n | SVP64:EXT000-063       |
  16
  17 Note that for the future SVP64Single Encoding (currently RESERVED3 and 4)
  18 it is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
  19 for which bits 8-31 can be zero (termed `scalar identity behaviour`). This
  20 prohibition allows SVP64Single to share its Encoding space with Scalar
  21 Ext232-263 and Scalar EXT300-363.
  22
  23 Also that RESERVED1 and 2 are candidates for future Major opcode
  24 areas EXT200-231 and EXT300-363 respectively, however as RESERVED areas
  25 they may equally be allocated entirely differently.
  26
  27 *Architectural Resource Allocation Note: **under no circumstances** must
  28 different Defined Words be allocated within any `EXT{z}` prefixed
  29 or unprefixed space for a given value of `z`. Even if UnVectoriseable
  30 an instruction Defined Word space must have the exact same Instruction
  31 and exact same Instruction Encoding in all spaces being RESERVED - Illegal
  32 Instruction Trap - if UnVectoriseable) or not be allocated at all.
  33 This is required as an inviolate hard rule governing Primary Opcode 9
  34 that may not be revoked under any circumstances. A useful way to think
  35 of this is that the Prefix Encoding is, like the 8086 REP instruction,
  36 an independent 32-bit Defined Word. The only semi-exceptions are
  37 the Post-Increment Mode of LD/ST-Update and Vectorised Branch-Conditional.*
  38
  39 Encoding spaces and their potential are illustrated:
  40
  41 | Encoding | Available bits | Scalar | Vectoriseable | SVP64Single  |
  42 |----------|----------------|--------|---------------|--------------|
  43 |EXT000-063| 32             | yes    | yes           |yes           |
  44 |EXT100-163| 64             | yes    | no            |no            |
  45 |RESERVED2 | 57             | N/A    |not applicable |not applicable|
  46 |EXT232-263| 32             | yes    | yes           |yes           |
  47 |RESERVED1 | 32             | N/A    | no            |no            |
  48
  49 Notes:
  50
  51 * Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
  52   thus inherently UnVectoriseable as the EXT1xx prefix is 32-bit
  53   on top of an SVP64 prefix which is 32-bit on top of a Defined Word
  54   and the complexity at the Decoder becomes too great for High
  55   Performance Multi-Issue systems.
  56 * RESERVED2 presently remains unallocated as of yet and therefore its
  57   potential is not yet defined (Not Applicable).
  58 * RESERVED1 is also unallocated at present, but it is known in advance
  59   that the area is UnVectoriseable and also cannot be Prefixed with
  60   SVP64Single.
  61 * Considerable care is needed both on Architectural Resource Allocation
  62   as well as instruction design itself.  Once an instruction is allocated
  63   in an UnVectoriseable area it can never be Vectorised without providing
  64   an entirely new Encoding.
  65
  66 [[!tag standards]]
  67
  68 --------
  69
  70 \newpage{}
  71