openpower/sv/rfc/ls002/discussion.mdwn

   1 # Links
   2
   3 * [[sv/int_fp_mv]]
   4
   5 # Questions (09 oct 2022)
   6
   7 1. What is "BF16"?  It seems not to be mentioned in the architecture spec.
   8    The architecture spec (VSX chapter) defines two 16-bit binary FP formats.
   9    Judging by the way the RFC uses "BF16", I think it means what the VSX
  10    chapter calls "bfloat16", which has the exponent in the same bits as
  11    single format.  This should be clarified, and the corresponding format
  12    will need to be defined in Section 4.3.1 (Data Format).
  13 2. For fishmv, what happens if the value supplied in the FPR is not
  14    representable in single format?
  15 3. The first clause of the verbal description of fishmv seems to assume
  16    that the contents of the specified register were produced by fmvis.
  17    Is there any other use of fishmv?  If yes, the verbal description should
  18    be generalized.  If no, the wording should be explicit about this use.
  19 4. The instruction names and mnemonics should be more consistent with the
  20    architecture spec.  In particular, the architecture spec tends to use
  21    "Move" for instructions that transfer data between registers.  Here are
  22    two approaches.
  23    a. Model the instructions on li (Load Immediate), an extended mnemonic for
  24       addi.
  25         fmvis --> Floating Load Immediate Single (flis)
  26         fishmv --> Floating Load Immediate Single Lower (flisl)
  27       Under this approach the new instructions would belong in their own
  28       3-level section, after Section 4.6.4 (Floating-Point Load and Store
  29       Double Pair Instructions).
  30    b. Model the instructions on lxvkq (and the existing FP Load instructions)
  31         fmvis --> Load Floating-Point Single Immediate (lfsi)
  32         fishmv --> Load Floating-Point Single Immediate Lower (lfsil)
  33       Under this approach the new instructions would belong in Section 4.6.2
  34       (Floating-Point Load Instructions), with the Load Floating-Point
  35       Single instructions.
  36    I prefer (a), because I think it's confusing to treat these instructions,
  37    which don't access storage, like instructions that do access storage.
  38
  39 Other:
  40
  41 1. The RFC should be based on the current version of the architecture,
  42    which is V. 3.1B.  I believe this has no effect on the substance of the
  43    RFC.  But it affects the identities of the instruction-list appendices,
  44   which in V. 3.1B are E, F, G, and H.
  45 2. Additional affected sections are 1.6.1.6 (additional line for DX-form),
  46    1.6.2 (additional use for d0,d1,d2), and Appendix D (Opcode Maps).
  47 3. Does the last line of the Summary apply to both instructions or just to
  48    fishmv?  I can see why you would want a prefixed version of fmvis, which
  49    would supply the entire 32-bit FP single format value and avoid the need
  50    for fishmv.  Why would you want a prefixed version of fishmv?
  51 4. The Motivation says "Even clearing an FPR to zero presently requires Load".
  52    What about fsub FRT,FRA,FRA?
  53 5. "FRS" for both instructions should be changed to "FRT".  ("FRS" normally
  54    specifies a source register; see Section 1.6.2.  I understand that for
  55    fishmv the specified register is both source and target.  But "TX,T"
  56    provides precedent for using the "target form" of register specification
  57    for such cases.)
  58 6. The RTL for fmvis should use left arrow for assignment.
  59 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
  60    lower-case versions thereof, for the 32-bit and 64-bit binary FP formats.
  61    The RFC's "FP32" and "FP64" (and lower case of same) should be made
  62    consistent with this usage.
  63 8. More generally, the style of the verbal description for both instructions
  64    should be made more consistent with the style used in the architecture
  65    spec.
  66 9. In the first clause of the verbal description of fishmv I think "inserted
  67    into FRS" should be "inserted into the low-order half of the single-
  68    format value corresponding to the contents of FRT".
  69    A similar change should be made in the second sentence of the next
  70    paragraph.
  71 10. The paragraph before the Programming Note in the fishmv description
  72    says "This is strategically similar to how li combined with oris is used
  73    to construct 32-bit Integers".  li combined with oris works only if bit 16
  74    of the desired 32-bit integer is 0.  (A better way to construct a 32-bit
  75    integer is to use pli (extended mnemonic for paddi).)