openpower/sv/rfc/ls002/discussion.mdwn

   1 # Links
   2
   3 * [[sv/int_fp_mv]]
   4
   5 # Questions (09 oct 2022)
   6
   7 **
   8 1. What is "BF16"?  It seems not to be mentioned in the architecture spec.
   9    The architecture spec (VSX chapter) defines two 16-bit binary FP formats.
  10    Judging by the way the RFC uses "BF16", I think it means what the VSX
  11    chapter calls "bfloat16", which has the exponent in the same bits as
  12    single format.  This should be clarified, and the corresponding format
  13    will need to be defined in Section 4.3.1 (Data Format).
  14 **
  15
  16 BF16 seems to be an equally commonly used term for bfloat16, yes.
  17
  18 **
  19 2. For fishmv, what happens if the value supplied in the FPR is not
  20    representable in single format?
  21 **
  22
  23 I'm assuming you're asking what happens if something like `f3 = 0x0080_0000_0000_0001` and `fishmv f3, 0xABCD` is executed:
  24 Exactly the same thing as if the FPR value isn't representable in f32 format for stfs -- the value stored is defined by the `SINGLE` pseudo-code function, no fp status bits are set. Likewise, the input f32 value for fishmv is determined by the `SINGLE` pseudo-code function, no fp status bits are set, fishmv then replaces the lower 16 bits of the f32 value with the immediate, then converts the resulting f32 back to f64 using `DOUBLE` and stores it in FRT.
  25
  26 Ultimately, these are immediates, statically-compiled.  if the developer
  27 wants "invalid" data, statically-compiled into a binary, it is reasonable
  28 to assume they have good reasons for doing so.
  29
  30 **
  31 3. The first clause of the verbal description of fishmv seems to assume
  32    that the contents of the specified register were produced by fmvis.
  33    Is there any other use of fishmv?  If yes, the verbal description should
  34    be generalized.  If no, the wording should be explicit about this use.
  35 **
  36
  37 given that the bits are spread out in `DOUBLE()` format it seems unlikely.
  38 if the bits were placed contiguously (sequentially) then it would indeed
  39 be a different matter: temporary storage for constants to be transferred
  40 directly (unmodified) to GPRs for example.  but DOUBLE() formatting
  41 makes that not possible unfortunately.
  42
  43 however alternative uses by programmers cannot be ruled out. it may
  44 be the case that despite the format being DOUBLE() there is in fact
  45 an FPR->GPR transfer instruction that can at least get the 32-bits
  46 of immediate back out as a contiguous undamaged block.  thus adding
  47 notes that may turn out to be restrictive is inadviseable.
  48
  49 **
  50 4. The instruction names and mnemonics should be more consistent with the
  51    architecture spec.  In particular, the architecture spec tends to use
  52    "Move" for instructions that transfer data between registers.  Here are
  53    two approaches.
  54 **
  55
  56 ```
  57    a. Model the instructions on li (Load Immediate), an extended mnemonic for
  58       addi.
  59         fmvis --> Floating Load Immediate Single (flis)
  60         fishmv --> Floating Load Immediate Single Lower (flisl)
  61       Under this approach the new instructions would belong in their own
  62       3-level section, after Section 4.6.4 (Floating-Point Load and Store
  63       Double Pair Instructions).
  64
  65    b. Model the instructions on lxvkq (and the existing FP Load instructions)
  66         fmvis --> Load Floating-Point Single Immediate (lfsi)
  67         fishmv --> Load Floating-Point Single Immediate Lower (lfsil)
  68       Under this approach the new instructions would belong in Section 4.6.2
  69       (Floating-Point Load Instructions), with the Load Floating-Point
  70       Single instructions.
  71
  72    I prefer (a), because I think it's confusing to treat these instructions,
  73    which don't access storage, like instructions that do access storage.
  74 ```
  75
  76 the fact that they bypass D-Cache and correspondingly raise no flags or
  77 exceptions is the connection to `ld`.  despite that i like (a) as well
  78 although for purely non-technical reasons (more "memorable") i (Luke) do love
  79 the two mnemonics `flis fishmv` :)
  80
  81 we picked "s" on the end of `fmvis` (`flis`) because it is "shifted"
  82 (like `oris`), not "single". this was accidentally left out of the initial RFC submission.
  83
  84 Other:
  85
  86 **
  87 1. The RFC should be based on the current version of the architecture,
  88    which is V. 3.1B.  I believe this has no effect on the substance of the
  89    RFC.  But it affects the identities of the instruction-list appendices,
  90   which in V. 3.1B are E, F, G, and H.
  91 **
  92
  93 acknowledged.  will edit. done.
  94
  95 **
  96 2. Additional affected sections are 1.6.1.6 (additional line for DX-form),
  97    1.6.2 (additional use for d0,d1,d2), and Appendix D (Opcode Maps).
  98 **
  99
 100 ditto. TODO.
 101
 102 missed the addition to 1.6.1.6 (DX-Form).  TODO
 103
 104 **
 105 3. Does the last line of the Summary apply to both instructions or just to
 106    fishmv?  I can see why you would want a prefixed version of fmvis, which
 107    would supply the entire 32-bit FP single format value and avoid the need
 108    for fishmv.  Why would you want a prefixed version of fishmv?
 109 **
 110
 111 the more interesting initial question is, "why no `pflis`?" and
 112 the answer to that is "because flis and fishmv do exactly the same
 113 job in exactly the same amount of bits" (64).
 114 `flis` fills in a BF16, `fishmv` extends to an FP32,
 115 and `pflis` would fill in an FP32 in exactly the same amount
 116 of space, making it a redundant encoding.  this just leaves the
 117 purpose of `pfishmv` to be to extend (fill) an FP32 out to an FP64.
 118
 119 that said: the next phase of whether it is worthwhile is to count the
 120 I/D-Cache usage.
 121 the analysis counting instructions and D-Cache Loads actually shows
 122 that whilst the initial idea for `pfishmv` would be to fill in the
 123 remaining mantissa and high exponent bits to complete a full FP64,
 124 the cost of doing so is:
 125
 126 * 1x32 flis
 127 * 1x32 fishmv
 128 * 1x64 pfishmv
 129
 130 which totals QTY 4of 32-bits (across I-Cache) which is actually *more* than just `lfd`,
 131 which is only QTY 3of 32-bits (across both I-Cache and D-Cache).
 132 the only technical reason therefore is
 133 to avoid D-Cache entirely, just like the 5-instruction sequence
 134 that writes a 64-bit GPR only from immediates
 135 (li, oris, rldicl, li, oris) although that is justifiable
 136 as a critical means of bootstrapping (constructing 64 bit addresses)
 137
 138 **
 139 4. The Motivation says "Even clearing an FPR to zero presently requires Load".
 140    What about fsub FRT,FRA,FRA?
 141 **
 142
 143 That doesn't actually clear FRT to zero because `NaN - NaN` and
 144 `Inf - Inf` both equal `NaN`, not zero. Also, with "round to -inf",
 145 0 - 0 produces -0, not 0.  Thus use of `fsub` is critically
 146 dependent on the contents of registers and status flags, where
 147 `flis` is not.
 148
 149 **
 150 5. "FRS" for both instructions should be changed to "FRT".  ("FRS" normally
 151    specifies a source register; see Section 1.6.2.  I understand that for
 152    fishmv the specified register is both source and target.  But "TX,T"
 153    provides precedent for using the "target form" of register specification
 154    for such cases.)
 155 6. The RTL for fmvis should use left arrow for assignment.
 156 **
 157
 158 RTL error corrected. ack on FRT.
 159
 160 **
 161 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
 162    lower-case versions thereof, for the 32-bit and 64-bit binary FP formats.
 163    The RFC's "FP32" and "FP64" (and lower case of same) should be made
 164    consistent with this usage.
 165 **
 166
 167 acknowledged. TODO.
 168
 169 **
 170 8. More generally, the style of the verbal description for both instructions
 171    should be made more consistent with the style used in the architecture
 172    spec.
 173 **
 174
 175 yes Paul kindly gave advice on that.
 176
 177 **
 178 9. In the first clause of the verbal description of fishmv I think "inserted
 179    into FRS" should be "inserted into the low-order half of the single-
 180    format value corresponding to the contents of FRT".
 181    A similar change should be made in the second sentence of the next
 182    paragraph.
 183 **
 184
 185 ack. TODO.
 186
 187 **
 188 10. The paragraph before the Programming Note in the fishmv description
 189    says "This is strategically similar to how li combined with oris is used
 190    to construct 32-bit Integers".  li combined with oris works only if bit 16
 191    of the desired 32-bit integer is 0.  (A better way to construct a 32-bit
 192    integer is to use pli (extended mnemonic for paddi).)
 193 **
 194
 195 it is unlikely that we (Libre-SOC) will initially implement any of v3.1
 196 64-bit prefixing (it cannot be Vectorised, resulting unacceptably in
 197 96-bit instructions which we decided is too much). that said, the LD
 198 addressing immediate extended range is extremely useful
 199 (along with the PC-relative modes and also other instructions
 200 such as paddi).
 201
 202 bottom line we have not yet given much thought to using any v3.1 Scalar
 203 Prefixed instructions, at all, so don't even know most of what they do.
 204
 205 that said: if `paddi` puts 32-bits into a GPR, and does so in 64 bits,
 206 is it not similarly redundant i.e. exactly the same amount of space
 207 used as two 32-bit instructions?  if `paddi` puts *more* than 32 bits
 208 into a GPR then it is not the same and would not make a comparative
 209 analogy as a Programmer's Note.
 210