openpower/sv/rfc/ls002/discussion.mdwn

   1 # Links
   2
   3 * [[sv/int_fp_mv]]
   4
   5 # v3.1 Prefixed instructions
   6
   7 **PREFIXED INSTRUCTIONS ARE 100% OUT OF SCOPE OF THIS RFC**.
   8
   9 please do not extend the scope of this RFC beyond the two
  10 32-bit instructions.
  11
  12 # Questions (09 oct 2022)
  13
  14 **Substantive or semi-substantive:**
  15
  16 **
  17 1. What is "BF16"?  It seems not to be mentioned in the architecture spec.
  18    The architecture spec (VSX chapter) defines two 16-bit binary FP formats.
  19    Judging by the way the RFC uses "BF16", I think it means what the VSX
  20    chapter calls "bfloat16", which has the exponent in the same bits as
  21    single format.  This should be clarified, and the corresponding format
  22    will need to be defined in Section 4.3.1 (Data Format).
  23 **
  24
  25 BF16 seems to be an equally commonly used term for bfloat16, yes.
  26
  27 **
  28 2. For fishmv, what happens if the value supplied in the FPR is not
  29    representable in single format?
  30 **
  31
  32 I'm assuming you're asking what happens if something like `f3 = 0x0080_0000_0000_0001` and `fishmv f3, 0xABCD` is executed:
  33 Exactly the same thing as if the FPR value isn't representable in f32 format for stfs -- the value stored is defined by the `SINGLE` pseudo-code function, no fp status bits are set. Likewise, the input f32 value for fishmv is determined by the `SINGLE` pseudo-code function, no fp status bits are set, fishmv then replaces the lower 16 bits of the f32 value with the immediate, then converts the resulting f32 back to f64 using `DOUBLE` and stores it in FRT.
  34
  35 Ultimately, these are immediates, statically-compiled.  if the developer
  36 wants "invalid" data, statically-compiled into a binary, it is reasonable
  37 to assume they have good reasons for doing so.
  38
  39 **
  40 3. The first clause of the verbal description of fishmv seems to assume
  41    that the contents of the specified register were produced by fmvis.
  42    Is there any other use of fishmv?  If yes, the verbal description should
  43    be generalized.  If no, the wording should be explicit about this use.
  44 **
  45
  46 given that the bits are spread out in `DOUBLE()` format it seems unlikely.
  47 if the bits were placed contiguously (sequentially) then it would indeed
  48 be a different matter: temporary storage for constants to be transferred
  49 directly (unmodified) to GPRs for example.  but DOUBLE() formatting
  50 makes that not possible unfortunately.
  51
  52 however alternative uses by programmers cannot be ruled out. it may
  53 be the case that despite the format being DOUBLE() there is in fact
  54 an FPR->GPR transfer instruction that can at least get the 32-bits
  55 of immediate back out as a contiguous undamaged block.  thus adding
  56 notes that may turn out to be restrictive is inadviseable.
  57
  58 **
  59 4. The instruction names and mnemonics should be more consistent with the
  60    architecture spec.  In particular, the architecture spec tends to use
  61    "Move" for instructions that transfer data between registers.  Here are
  62    two approaches.
  63 **
  64
  65 ```
  66    a. Model the instructions on li (Load Immediate), an extended mnemonic for
  67       addi.
  68         fmvis --> Floating Load Immediate Single (flis)
  69         fishmv --> Floating Load Immediate Single Lower (flisl)
  70       Under this approach the new instructions would belong in their own
  71       3-level section, after Section 4.6.4 (Floating-Point Load and Store
  72       Double Pair Instructions).
  73
  74    b. Model the instructions on lxvkq (and the existing FP Load instructions)
  75         fmvis --> Load Floating-Point Single Immediate (lfsi)
  76         fishmv --> Load Floating-Point Single Immediate Lower (lfsil)
  77       Under this approach the new instructions would belong in Section 4.6.2
  78       (Floating-Point Load Instructions), with the Load Floating-Point
  79       Single instructions.
  80
  81    I prefer (a), because I think it's confusing to treat these instructions,
  82    which don't access storage, like instructions that do access storage.
  83 ```
  84
  85 the fact that they bypass D-Cache and correspondingly raise no flags or
  86 exceptions is the connection to `ld`.  despite that i like (a) as well
  87 although for purely non-technical reasons (more "memorable") i (Luke) do love
  88 the two mnemonics `flis fishmv` :)
  89
  90 we picked "s" on the end of `fmvis` (`flis`) because it is "shifted"
  91 (like `oris`), not "single".
  92
  93 **Other:**
  94
  95 **
  96 1. The RFC should be based on the current version of the architecture,
  97    which is V. 3.1B.  I believe this has no effect on the substance of the
  98    RFC.  But it affects the identities of the instruction-list appendices,
  99   which in V. 3.1B are E, F, G, and H.
 100 **
 101
 102 acknowledged.  will edit. done v3.1B, TODO EFGH.
 103
 104 **
 105 2. Additional affected sections are 1.6.1.6 (additional line for DX-form),
 106    1.6.2 (additional use for d0,d1,d2), and Appendix D (Opcode Maps).
 107 **
 108
 109 ditto. TODO.
 110
 111 missed the addition to 1.6.1.6 (DX-Form).  TODO
 112
 113 **
 114 3. Does the last line of the Summary apply to both instructions or just to
 115    fishmv?  I can see why you would want a prefixed version of fmvis, which
 116    would supply the entire 32-bit FP single format value and avoid the need
 117    for fishmv.  Why would you want a prefixed version of fishmv?
 118 **
 119
 120 the more interesting initial question is, "why no `pflis`?" and
 121 the answer to that is "because flis and fishmv do exactly the same
 122 job in exactly the same amount of bits" (64).
 123 `flis` fills in a BF16, `fishmv` extends to an FP32,
 124 and `pflis` would fill in an FP32 in exactly the same amount
 125 of space, making it a redundant encoding.  this just leaves the
 126 purpose of `pfishmv` to be to extend (fill) an FP32 out to an FP64.
 127
 128 that said: the next phase of whether it is worthwhile is to count the
 129 I/D-Cache usage.
 130 the analysis counting instructions and D-Cache Loads actually shows
 131 that whilst the initial idea for `pfishmv` would be to fill in the
 132 remaining mantissa and high exponent bits to complete a full FP64,
 133 the cost of doing so is:
 134
 135 * 1x32 flis
 136 * 1x32 fishmv
 137 * 1x64 pfishmv
 138
 139 which totals QTY 4of 32-bits (across I-Cache) which is actually *more* than just `lfd`,
 140 which is only QTY 3of 32-bits (across both I-Cache and D-Cache).
 141 the only technical reason therefore is
 142 to avoid D-Cache entirely, just like the 5-instruction sequence
 143 that writes a 64-bit GPR only from immediates
 144 (li, oris, rldicl, li, oris) although that is justifiable
 145 as a critical means of bootstrapping (constructing 64 bit addresses)
 146
 147 **
 148 4. The Motivation says "Even clearing an FPR to zero presently requires Load".
 149    What about fsub FRT,FRA,FRA?
 150 **
 151
 152 That doesn't actually clear FRT to zero because `NaN - NaN` and
 153 `Inf - Inf` both equal `NaN`, not zero. Also, with "round to -inf",
 154 0 - 0 produces -0, not 0.  Thus use of `fsub` is critically
 155 dependent on the contents of registers and status flags, where
 156 `flis` is not.
 157
 158 **
 159 5. "FRS" for both instructions should be changed to "FRT".  ("FRS" normally
 160    specifies a source register; see Section 1.6.2.  I understand that for
 161    fishmv the specified register is both source and target.  But "TX,T"
 162    provides precedent for using the "target form" of register specification
 163    for such cases.)
 164 6. The RTL for fmvis should use left arrow for assignment.
 165 **
 166
 167 RTL error corrected. ack on FRT.
 168
 169 **
 170 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
 171    lower-case versions thereof, for the 32-bit and 64-bit binary FP formats.
 172    The RFC's "FP32" and "FP64" (and lower case of same) should be made
 173    consistent with this usage.
 174 **
 175
 176 acknowledged. TODO.
 177
 178 **
 179 8. More generally, the style of the verbal description for both instructions
 180    should be made more consistent with the style used in the architecture
 181    spec.
 182 **
 183
 184 yes Paul kindly gave advice on that.
 185
 186 **
 187 9. In the first clause of the verbal description of fishmv I think "inserted
 188    into FRS" should be "inserted into the low-order half of the single-
 189    format value corresponding to the contents of FRT".
 190    A similar change should be made in the second sentence of the next
 191    paragraph.
 192 **
 193
 194 ack. TODO.
 195
 196 **
 197 10. The paragraph before the Programming Note in the fishmv description
 198    says "This is strategically similar to how li combined with oris is used
 199    to construct 32-bit Integers".  li combined with oris works only if bit 16
 200    of the desired 32-bit integer is 0.  (A better way to construct a 32-bit
 201    integer is to use pli (extended mnemonic for paddi).)
 202 **
 203
 204 it is unlikely that we (Libre-SOC) will initially implement any of v3.1
 205 64-bit prefixing (it cannot be Vectorised, resulting unacceptably in
 206 96-bit instructions which we decided is too much). that said, the LD
 207 addressing immediate extended range is extremely useful
 208 (along with the PC-relative modes and also other instructions
 209 such as paddi).
 210
 211 bottom line we have not yet given much thought to using any v3.1 Scalar
 212 Prefixed instructions, at all, so don't even know most of what they do.
 213
 214 that said: if `paddi` puts 32-bits into a GPR, and does so in 64 bits,
 215 is it not similarly redundant i.e. exactly the same amount of space
 216 used as two 32-bit instructions?  if `paddi` puts *more* than 32 bits
 217 into a GPR then it is not the same and would not make a suitable
 218 comparative analogy as a Programmer's Note.
 219