openpower/sv/rfc/ls002/discussion.mdwn

   1 # Links
   2
   3 * [[sv/int_fp_mv]]
   4
   5 # Questions (09 oct 2022)
   6
   7 **
   8 1. What is "BF16"?  It seems not to be mentioned in the architecture spec.
   9    The architecture spec (VSX chapter) defines two 16-bit binary FP formats.
  10    Judging by the way the RFC uses "BF16", I think it means what the VSX
  11    chapter calls "bfloat16", which has the exponent in the same bits as
  12    single format.  This should be clarified, and the corresponding format
  13    will need to be defined in Section 4.3.1 (Data Format).
  14 **
  15
  16 BF16 seems to be an equally commonly used term for bfloat16, yes.
  17
  18 **
  19 2. For fishmv, what happens if the value supplied in the FPR is not
  20    representable in single format?
  21 **
  22
  23 exactly the same thing as if `fld` were used to load an "unrepresentable"
  24 value: nothing.  if `fld` raised flags or exceptions then so would (should)
  25 `fmvis`.
  26
  27 **
  28 3. The first clause of the verbal description of fishmv seems to assume
  29    that the contents of the specified register were produced by fmvis.
  30    Is there any other use of fishmv?  If yes, the verbal description should
  31    be generalized.  If no, the wording should be explicit about this use.
  32 **
  33
  34 given that the bits are spread out in `DOUBLE()` format it seems unlikely.
  35 if the bits were placed contiguously (sequentially) then it would indeed
  36 be a different matter.
  37
  38 **
  39 4. The instruction names and mnemonics should be more consistent with the
  40    architecture spec.  In particular, the architecture spec tends to use
  41    "Move" for instructions that transfer data between registers.  Here are
  42    two approaches.
  43 **
  44
  45 ```
  46    a. Model the instructions on li (Load Immediate), an extended mnemonic for
  47       addi.
  48         fmvis --> Floating Load Immediate Single (flis)
  49         fishmv --> Floating Load Immediate Single Lower (flisl)
  50       Under this approach the new instructions would belong in their own
  51       3-level section, after Section 4.6.4 (Floating-Point Load and Store
  52       Double Pair Instructions).
  53
  54    b. Model the instructions on lxvkq (and the existing FP Load instructions)
  55         fmvis --> Load Floating-Point Single Immediate (lfsi)
  56         fishmv --> Load Floating-Point Single Immediate Lower (lfsil)
  57       Under this approach the new instructions would belong in Section 4.6.2
  58       (Floating-Point Load Instructions), with the Load Floating-Point
  59       Single instructions.
  60
  61    I prefer (a), because I think it's confusing to treat these instructions,
  62    which don't access storage, like instructions that do access storage.
  63 ```
  64
  65 the fact that they bypass D-Cache and correspondingly raise no flags or
  66 exceptions is the connection to `ld`.  despite that i like (a) as well
  67 although for purely non-technical reasons (more "memorable") i do love
  68 the two mnemonics `flis fishmv` :)
  69
  70 we picked "s" on the end of `fmvis` (`flis`) because it is "shifted"
  71 (like `oris`)
  72
  73 Other:
  74
  75 **
  76 1. The RFC should be based on the current version of the architecture,
  77    which is V. 3.1B.  I believe this has no effect on the substance of the
  78    RFC.  But it affects the identities of the instruction-list appendices,
  79   which in V. 3.1B are E, F, G, and H.
  80 **
  81
  82 acknowledged.  will edit. done.
  83
  84 **
  85 2. Additional affected sections are 1.6.1.6 (additional line for DX-form),
  86    1.6.2 (additional use for d0,d1,d2), and Appendix D (Opcode Maps).
  87 **
  88
  89 ditto. TODO.
  90
  91 **
  92 3. Does the last line of the Summary apply to both instructions or just to
  93    fishmv?  I can see why you would want a prefixed version of fmvis, which
  94    would supply the entire 32-bit FP single format value and avoid the need
  95    for fishmv.  Why would you want a prefixed version of fishmv?
  96 **
  97
  98 the analysis counting instructions and D-Cache Loads actually shows
  99 that whilst the initial idea for `pfmvis` would be to fill in the
 100 remaining mantissa and high exponent bits to complete a full FP64,
 101 the cost of doing so is:
 102
 103 * 1x32 flis
 104 * 1x32 fishmv
 105 * 1x64 pfishmv
 106
 107 which is QTY 8 bytes which is actually *more* than just `fld`,
 108 which is only QTY 6 bytes.  the only technical reason therefore is
 109 to avoid D-Cache entirely, just like the 5-instruction sequence
 110 that writes a 64-bit GPR only from immediates
 111 (li, oris, rldicl, li, oris) although that is justifiable
 112 as a critical means of bootstrapping (constructing 64 bit addresses)
 113
 114 **
 115 4. The Motivation says "Even clearing an FPR to zero presently requires Load".
 116    What about fsub FRT,FRA,FRA?
 117 **
 118
 119 didn't know about it! although technically that reads registers
 120 (unless micro-code-redirected to an internal zeroing operation)
 121
 122 **
 123 5. "FRS" for both instructions should be changed to "FRT".  ("FRS" normally
 124    specifies a source register; see Section 1.6.2.  I understand that for
 125    fishmv the specified register is both source and target.  But "TX,T"
 126    provides precedent for using the "target form" of register specification
 127    for such cases.)
 128 6. The RTL for fmvis should use left arrow for assignment.
 129 **
 130
 131 RTL error corrected. ack on FRT.
 132
 133 **
 134 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
 135    lower-case versions thereof, for the 32-bit and 64-bit binary FP formats.
 136    The RFC's "FP32" and "FP64" (and lower case of same) should be made
 137    consistent with this usage.
 138 **
 139
 140 acknowledged. TODO.
 141
 142 **
 143 8. More generally, the style of the verbal description for both instructions
 144    should be made more consistent with the style used in the architecture
 145    spec.
 146 **
 147
 148 yes Paul kindly gave advice on that.
 149
 150 **
 151 9. In the first clause of the verbal description of fishmv I think "inserted
 152    into FRS" should be "inserted into the low-order half of the single-
 153    format value corresponding to the contents of FRT".
 154    A similar change should be made in the second sentence of the next
 155    paragraph.
 156 **
 157
 158 ack. TODO.
 159
 160 **
 161 10. The paragraph before the Programming Note in the fishmv description
 162    says "This is strategically similar to how li combined with oris is used
 163    to construct 32-bit Integers".  li combined with oris works only if bit 16
 164    of the desired 32-bit integer is 0.  (A better way to construct a 32-bit
 165    integer is to use pli (extended mnemonic for paddi).)
 166 **
 167
 168 it is extremely unlikely that we (Libre-SOC) will implement any of v3.1
 169 64-bit prefixing (it cannot be Vectorised, resulting unacceptably in
 170 96-bit instructions so what is the point). that said the LD
 171 addressing immediate extended range is extremely useful.
 172
 173 bottom line we have given almost no thought to using any v3.1 Scalar
 174 Prefixed instructions, at all, so don't even know 99% of what they do.