openpower/sv/rfc/ls002/discussion.mdwn

   1 # Links
   2
   3 * [[sv/int_fp_mv]]
   4
   5 # Questions (09 oct 2022)
   6
   7 **
   8 1. What is "BF16"?  It seems not to be mentioned in the architecture spec.
   9    The architecture spec (VSX chapter) defines two 16-bit binary FP formats.
  10    Judging by the way the RFC uses "BF16", I think it means what the VSX
  11    chapter calls "bfloat16", which has the exponent in the same bits as
  12    single format.  This should be clarified, and the corresponding format
  13    will need to be defined in Section 4.3.1 (Data Format).
  14 **
  15
  16 BF16 seems to be an equally commonly used term for bfloat16, yes.
  17
  18 **
  19 2. For fishmv, what happens if the value supplied in the FPR is not
  20    representable in single format?
  21 **
  22
  23 I'm assuming you're asking what happens if something like `f3 = 0x0080_0000_0000_0001` and `fishmv f3, 0xABCD` is executed:
  24 Exactly the same thing as if the FPR value isn't representable in f32 format for stfs -- the value stored is defined by the `SINGLE` pseudo-code function, no fp status bits are set. Likewise, the input f32 value for fishmv is determined by the `SINGLE` pseudo-code function, no fp status bits are set, fishmv then replaces the lower 16 bits of the f32 value with the immediate, then converts the resulting f32 back to f64 using `DOUBLE` and stores it in FRT.
  25
  26 **
  27 3. The first clause of the verbal description of fishmv seems to assume
  28    that the contents of the specified register were produced by fmvis.
  29    Is there any other use of fishmv?  If yes, the verbal description should
  30    be generalized.  If no, the wording should be explicit about this use.
  31 **
  32
  33 given that the bits are spread out in `DOUBLE()` format it seems unlikely.
  34 if the bits were placed contiguously (sequentially) then it would indeed
  35 be a different matter: temporary storage for constants to be transferred
  36 directly (unmodified) to GPRs for example.  but DOUBLE() formatting
  37 makes that not possible unfortunately.
  38
  39 **
  40 4. The instruction names and mnemonics should be more consistent with the
  41    architecture spec.  In particular, the architecture spec tends to use
  42    "Move" for instructions that transfer data between registers.  Here are
  43    two approaches.
  44 **
  45
  46 ```
  47    a. Model the instructions on li (Load Immediate), an extended mnemonic for
  48       addi.
  49         fmvis --> Floating Load Immediate Single (flis)
  50         fishmv --> Floating Load Immediate Single Lower (flisl)
  51       Under this approach the new instructions would belong in their own
  52       3-level section, after Section 4.6.4 (Floating-Point Load and Store
  53       Double Pair Instructions).
  54
  55    b. Model the instructions on lxvkq (and the existing FP Load instructions)
  56         fmvis --> Load Floating-Point Single Immediate (lfsi)
  57         fishmv --> Load Floating-Point Single Immediate Lower (lfsil)
  58       Under this approach the new instructions would belong in Section 4.6.2
  59       (Floating-Point Load Instructions), with the Load Floating-Point
  60       Single instructions.
  61
  62    I prefer (a), because I think it's confusing to treat these instructions,
  63    which don't access storage, like instructions that do access storage.
  64 ```
  65
  66 the fact that they bypass D-Cache and correspondingly raise no flags or
  67 exceptions is the connection to `ld`.  despite that i like (a) as well
  68 although for purely non-technical reasons (more "memorable") i (Luke) do love
  69 the two mnemonics `flis fishmv` :)
  70
  71 we picked "s" on the end of `fmvis` (`flis`) because it is "shifted"
  72 (like `oris`), not "single". this was accidentally left out of the initial RFC submission.
  73
  74 Other:
  75
  76 **
  77 1. The RFC should be based on the current version of the architecture,
  78    which is V. 3.1B.  I believe this has no effect on the substance of the
  79    RFC.  But it affects the identities of the instruction-list appendices,
  80   which in V. 3.1B are E, F, G, and H.
  81 **
  82
  83 acknowledged.  will edit. done.
  84
  85 **
  86 2. Additional affected sections are 1.6.1.6 (additional line for DX-form),
  87    1.6.2 (additional use for d0,d1,d2), and Appendix D (Opcode Maps).
  88 **
  89
  90 ditto. TODO.
  91
  92 missed the addition to 1.6.1.6 (DX-Form).  TODO
  93
  94 **
  95 3. Does the last line of the Summary apply to both instructions or just to
  96    fishmv?  I can see why you would want a prefixed version of fmvis, which
  97    would supply the entire 32-bit FP single format value and avoid the need
  98    for fishmv.  Why would you want a prefixed version of fishmv?
  99 **
 100
 101 the more interesting initial question is, "why no `pflis`?" and
 102 the answer to that is "because flis and fishmv do exactly the same
 103 job in exactly the same amount of bits" (64).
 104 `flis` fills in a BF16, `fishmv` extends to an FP32,
 105 and `pflis` would fill in an FP32 in exactly the same amount
 106 of space, making it a redundant encoding.  this just leaves the
 107 purpose of `pfishmv` to be to extend (fill) an FP32 out to an FP64.
 108
 109 that said: the next phase of whether it is worthwhile is to count the
 110 I/D-Cache usage.
 111 the analysis counting instructions and D-Cache Loads actually shows
 112 that whilst the initial idea for `pfishmv` would be to fill in the
 113 remaining mantissa and high exponent bits to complete a full FP64,
 114 the cost of doing so is:
 115
 116 * 1x32 flis
 117 * 1x32 fishmv
 118 * 1x64 pfishmv
 119
 120 which totals QTY 4of 32-bits (across I-Cache) which is actually *more* than just `lfd`,
 121 which is only QTY 3of 32-bits (across both I-Cache and D-Cache).
 122 the only technical reason therefore is
 123 to avoid D-Cache entirely, just like the 5-instruction sequence
 124 that writes a 64-bit GPR only from immediates
 125 (li, oris, rldicl, li, oris) although that is justifiable
 126 as a critical means of bootstrapping (constructing 64 bit addresses)
 127
 128 **
 129 4. The Motivation says "Even clearing an FPR to zero presently requires Load".
 130    What about fsub FRT,FRA,FRA?
 131 **
 132
 133 That doesn't actually clear FRT to zero because `NaN - NaN` and
 134 `Inf - Inf` both equal `NaN`, not zero. Also, with "round to -inf",
 135 0 - 0 produces -0, not 0.  Thus use of `fsub` is critically
 136 dependent on the contents of registers and status flags, where
 137 `flis` is not.
 138
 139 **
 140 5. "FRS" for both instructions should be changed to "FRT".  ("FRS" normally
 141    specifies a source register; see Section 1.6.2.  I understand that for
 142    fishmv the specified register is both source and target.  But "TX,T"
 143    provides precedent for using the "target form" of register specification
 144    for such cases.)
 145 6. The RTL for fmvis should use left arrow for assignment.
 146 **
 147
 148 RTL error corrected. ack on FRT.
 149
 150 **
 151 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
 152    lower-case versions thereof, for the 32-bit and 64-bit binary FP formats.
 153    The RFC's "FP32" and "FP64" (and lower case of same) should be made
 154    consistent with this usage.
 155 **
 156
 157 acknowledged. TODO.
 158
 159 **
 160 8. More generally, the style of the verbal description for both instructions
 161    should be made more consistent with the style used in the architecture
 162    spec.
 163 **
 164
 165 yes Paul kindly gave advice on that.
 166
 167 **
 168 9. In the first clause of the verbal description of fishmv I think "inserted
 169    into FRS" should be "inserted into the low-order half of the single-
 170    format value corresponding to the contents of FRT".
 171    A similar change should be made in the second sentence of the next
 172    paragraph.
 173 **
 174
 175 ack. TODO.
 176
 177 **
 178 10. The paragraph before the Programming Note in the fishmv description
 179    says "This is strategically similar to how li combined with oris is used
 180    to construct 32-bit Integers".  li combined with oris works only if bit 16
 181    of the desired 32-bit integer is 0.  (A better way to construct a 32-bit
 182    integer is to use pli (extended mnemonic for paddi).)
 183 **
 184
 185 it is unlikely that we (Libre-SOC) will initially implement any of v3.1
 186 64-bit prefixing (it cannot be Vectorised, resulting unacceptably in
 187 96-bit instructions which we decided is too much). that said, the LD
 188 addressing immediate extended range is extremely useful
 189 (along with the PC-relative modes and also other instructions
 190 such as paddi).
 191
 192 bottom line we have not yet given much thought to using any v3.1 Scalar
 193 Prefixed instructions, at all, so don't even know most of what they do.
 194
 195 that said: if `paddi` puts 32-bits into a GPR, and does so in 64 bits,
 196 is it not similarly redundant i.e. exactly the same amount of space
 197 used as two 32-bit instructions?  if `paddi` puts *more* than 32 bits
 198 into a GPR then it is not the same and would not make a comparative
 199 analogy as a Programmer's Note.
 200