1 # RFC ls002.fmi v2 Floating-Point Load-Immediate
5 * <https://libre-soc.org/openpower/sv/int_fp_mv/#fmvis>
6 * <https://libre-soc.org/openpower/sv/rfc/ls002.fmi/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1092>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/87>
14 **Date**: 05 Oct 2022 v3 TODO
20 **Books and Section affected**:
23 Book I Scalar Floating-Point 4.6.2.1
24 Appendix E Power ISA sorted by opcode
25 Appendix F Power ISA sorted by version
26 Appendix G Power ISA sorted by Compliancy Subset
27 Appendix H Power ISA sorted by mnemonic
34 fmvis - Floating-Point Move Immediate, Shifted
35 fishmv - Floating-Point Immediate, Second-half Move
38 **Submitter**: Luke Leighton (Libre-SOC)
40 **Requester**: Libre-SOC
42 **Impact on processor**:
45 Addition of two new FPR-based instructions
48 **Impact on software**:
51 Requires support for new instructions in assembler, debuggers,
58 FPR, Floating-point, Load-immediate, BF16, bfloat16, BFP32
63 Similar to `lxvkq` but extended to a bfloat16 with one
64 32-bit instruction and a full FP32 in two 32-bit instructions
65 these instructions always save a Data Load and associated L1
66 and TLB lookup. Even quickly clearing an FPR to zero presently needs Load.
68 **Notes and Observations**:
70 1. There is no need for an Rc=1 variant because this is an immediate
71 loading instruction (an FPR equivalent to `li`)
72 2. There is no need for Special Registers (FP Flags) because this
73 is an immediate loading instruction. No FPR Load Operations
74 alter `FPSCR`, neither does `lxvkq`, and on that basis neither
75 should these instructions.
76 3. `fishmv` as a FRT-only Read-Modify-Write (instead of an unnecessary
77 FRT,FRA pair) saves five potential bits, making
78 the difference between a 5-bit XO (VA/DX-Form) and requiring an entire
83 Add the following entries to:
85 * the Appendices of Book I
86 * Instructions of Book I as a new Section 4.6.2.1
87 * DX-Form of Book I Section 1.6.1.6 and 1.6.2
88 * Floating-Point Data a Format of Book I Section 4.3.1
94 # Floating-Point Move Immediate
98 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |
99 |--------|------|-------|-------|-------|-----|---------|
100 | Major | FRT | d1 | d0 | XO | d2 | DX-Form |
105 bf16 <- d0 || d1 || d2 # create bfloat16 immediate
106 bfp32 <- bf16 || [0]*16 # convert bfloat16 to BFP32
107 FRT <- DOUBLE(bfp32) # convert BFP32 to BFP64
110 Special registers altered:
114 The value `D << 16` is interpreted as a 32-bit float, converted to a
115 64-bit float and written to `FRT`. This is equivalent to reinterpreting
116 `D` as a `bfloat16` and converting to 64-bit float.
121 fmvis f4, 0 # writes +0.0 to f4 (clears an FPR)
122 fmvis f4, 0x8000 # writes -0.0 to f4
123 fmvis f4, 0x3F80 # writes +1.0 to f4
124 fmvis f4, 0xBFC0 # writes -1.5 to f4
125 fmvis f4, 0x7FC0 # writes +qNaN to f4
126 fmvis f4, 0x7F80 # writes +Infinity to f4
127 fmvis f4, 0xFF80 # writes -Infinity to f4
128 fmvis f4, 0x3FFF # writes +1.9921875 to f4
131 # Floating-Point Immediate Second-Half Move
137 | 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |
138 |--------|------|-------|-------|-------|-----|---------|
139 | Major | FRT | d1 | d0 | XO | d2 | DX-Form |
144 n <- (FRT) # read FRT
145 bfp32 <- SINGLE(n) # convert to BFP32
146 bfp32[16:31] <- d0 || d1 || d2 # replace LSB half
147 FRT <- DOUBLE(bfp32) # convert back to BFP64
150 Special registers altered:
154 An additional 16-bits of immediate is
155 inserted into the low-order half of the single-format value
156 corresponding to the contents of FRT.
158 **This instruction performs a Read-Modify-Write on FRT.**
159 In hardware, `fishmv` may be macro-op-fused with `fmvis`.
162 The use of these two instructions is strategically similar to
163 how `li` combined with `oris` may be used to construct 32-bit Integers.
164 If a prior `fmvis` instruction had been used to
165 set the upper 16-bits from a BFP32 value, `fishmv` may be used
171 # these two combined instructions write 0x3f808000
172 # into f4 as a BFP32 to be converted to a BFP64.
173 # actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
174 # first the upper bits, happens to be +1.0
175 fmvis f4, 0x3F80 # writes +1.0 to f4
176 # now write the lower 16 bits of a BFP32
177 fishmv f4, 0x8000 # writes +1.00390625 to f4
187 Add the following to Book I, 1.6.1.6, DX-Form
190 |0 |6 |11 |16 |26 |31
191 | PO | FRT| d1| d0| XO|d2
194 Add `DX` to `FRT` Field in Book I, 1.6.2
198 Field used to specify an FPR to be used as a
203 # bfloat16 definition
205 Add the following to Book I, 4.3.1:
207 The format may be a 16-bit bfloat16, 32-bit single format for a
208 single-precision value...
210 The bfloat16 format is used as an immediate.
212 The structure of the bfloat16, single and double formats is shown below.
219 Figure #. Binary floating-point half-precision format (bfloat16)
223 Appendix E Power ISA sorted by opcode
224 Appendix F Power ISA sorted by version
225 Appendix G Power ISA sorted by Compliancy Subset
226 Appendix H Power ISA sorted by mnemonic
228 | Form | Book | Page | Version | mnemonic | Description |
229 |------|------|------|---------|----------|-------------|
230 | DX | I | # | 3.0B | fmvis | Floating-point Move Immediate, Shifted |
231 | DX | I | # | 3.0B | fishmv | Floating-point Immediate, Second-half Move |