1 # RFC ls006 FPR <-> GPR Move/Conversion
5 * <https://libre-soc.org/openpower/sv/int_fp_mv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls006.fpintmv/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1015>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/todo>
20 **Books and Section affected**: **UPDATE**
22 * Book I 4.6.5 Floating-Point Move Instructions
23 * Book I 4.6.7.2 Floating-Point Convert To/From Integer Instructions
24 * Appendix E Power ISA sorted by opcode
25 * Appendix F Power ISA sorted by version
26 * Appendix G Power ISA sorted by Compliancy Subset
27 * Appendix H Power ISA sorted by mnemonic
31 Single-precision Instructions added:
33 * `mffprs` -- Single-Precision Floating Move To GPR
34 * `mtfprs` -- Single-Precision Floating Move From GPR
35 * `ctfprs` -- Single-Precision Floating Convert From Integer In GPR
37 Identical (except Double-precision) Instructions added:
39 * `mffpr` -- Double-Precision Floating Move To GPR
40 * `mtfpr` -- Double-Precision Floating Move From GPR
41 * `cffpr` -- Double-Precision Floating Convert To Integer In GPR
42 * `ctfpr` -- Double-Precision Floating Convert From Integer In GPR
44 **Submitter**: Luke Leighton (Libre-SOC)
46 **Requester**: Libre-SOC
48 **Impact on processor**:
50 * Addition of three new Single-Precision GPR-FPR-based instructions
51 * Addition of four new Double-Precision GPR-FPR-based instructions
53 **Impact on software**:
55 * Requires support for new instructions in assembler, debuggers,
61 GPR, FPR, Move, Conversion, JavaScript
66 CPUs without VSX/VMX lack a way to efficiently transfer data between
67 FPRs and GPRs, they need to go through memory, this proposal adds more
68 efficient data transfer (both bitwise copy and Integer <-> FP conversion)
69 instructions that transfer directly between FPRs and GPRs without needing
72 IEEE 754 doesn't specify what results are obtained when converting a NaN
73 or out-of-range floating-point value to integer, so different programming
74 languages and ISAs have made different choices. Below is an overview
75 of the different variants, listing the languages and hardware that
76 implements each variant.
78 **Notes and Observations**:
80 * These instructions are present in many other ISAs.
81 * JavaScript rounding as one instruction saves 32 scalar instructions
82 including seven branch instructions.
83 * Both sets are orthogonal (no difference except being Single/Double).
84 This allows IBM to follow the pre-existing precedent of allocating
85 separate Major Opcodes (PO) for Double-precision and Single-precision
90 Add the following entries to:
92 * Book I 4.6.5 Floating-Point Move Instructions
93 * Book I 4.6.7.2 Floating-Point Convert To/From Integer Instructions
94 * Book I 1.6.1 and 1.6.2
100 [[!inline pages="openpower/sv/int_fp_mv/moves_and_conversions" raw=yes ]]
108 # Instruction Formats
110 Add the following entries to Book I 1.6.1.19 XO-FORM:
113 |0 |6 |11 |13 |16 |21 |22 |31 |
114 | PO | RT | IT | CVM | FRB | OE | XO | Rc |
117 Add the following entries to Book I 1.6.1.15 X-FORM:
120 |0 |6 |11 |13 |16 |21 |31 |
121 | PO | FRT | IT | // | RB | XO | Rc |
122 | PO | FRT | // | RB | XO | Rc |
123 | PO | RT | // | FRB | XO | Rc |
128 Add XO to FRB's Formats list in Book I 1.6.2 Word Instruction Fields.
130 Add XO to FRT's Formats list in Book I 1.6.2 Word Instruction Fields.
136 Field used to specify integer type for FPR <-> GPR conversions.
141 Field used to specify conversion mode for
142 integer -> floating-point conversion.
155 Appendix E Power ISA sorted by opcode
156 Appendix F Power ISA sorted by version
157 Appendix G Power ISA sorted by Compliancy Subset
158 Appendix H Power ISA sorted by mnemonic
160 |Form| Book | Page | Version | mnemonic | Description |
161 |----|------|------|---------|----------|-------------|
162 |VA | I | # | 3.2B |todo | |