1 # RFC ls008 SVP64 Management instructions
3 * Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
4 Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
5 * <https://libre-soc.org/openpower/sv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls008/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1089>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/123>
20 **Books and Section affected**:
23 Book I, new Scalar Chapter. (Or, new Book on "Zero-Overhead Loop Subsystem")
24 Appendix E Power ISA sorted by opcode
25 Appendix F Power ISA sorted by version
26 Appendix G Power ISA sorted by Compliancy Subset
27 Appendix H Power ISA sorted by mnemonic
33 setvl - Cray-style "Set Vector Length" instruction
34 svstep - Vertical-First Mode explicit Step and Status
37 **Submitter**: Luke Leighton (Libre-SOC)
39 **Requester**: Libre-SOC
41 **Impact on processor**:
44 Addition of two new "Zero-Overhead-Loop-Control" DSP-style Vector-style
45 Management Instructions which can be implemented extremely efficiently
46 and effectively by inserting an additional phase between Decode and Issue.
47 More complex designs are NOT adversely impacted and in fact greatly benefit
50 **Impact on software**:
53 Requires support for new instructions in assembler, debuggers,
60 Cray Supercomputing, Vectorization, Zero-Overhead-Loop-Control (ZOLC),
61 Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
62 Digital Signal Processing (DSP)
67 Power ISA is synonymous with Supercomputing and the early Supercomputers
68 (ETA-10, ILLIAC-IV, CDC200, Cray) had Vectorization. It is therefore anomalous
69 that Power ISA does not have Scalable Vectors. This presents the opportunity to
70 modernise Power ISA keeping it at the top of Supercomputing.
72 **Notes and Observations**:
74 1. SVP64 is very much designed for ultra-light-weight Embedded use-cases all the
75 way up to moving the bar of Supercomputing orders of magnitude above its present
76 perception, whilst retaining at all times Sequential Programming Execution.
77 2. This proposal is the **base** for further Extensions. These include
78 extending SVP64 onto the Scalar VSX instructions (with a **LONG TERM** view in 10+ years
79 to deprecating the PackedSIMD aspects of VSX), to be discussed at a later
80 time, the potential for extending VSX registers to 128 or beyond, and Arithmetic
81 operations to a runtime-selectable choice of 128-bit, 256-bit, 512-bit or 1024-bit.
82 3. Massive reductions in instruction count of between 2x and 20x have been demonstrated
83 with SVP64, which is far beyond anything ever achieved by any *general-purpose*
84 ISA Extension added to any ISA in the history of Computing.
88 Add the following entries to:
90 * Section 1.3.2 Notation
91 * the Appendices of Book I
92 * Instructions of Book I as a new Section
93 * SVL-Form of Book I Section 1.6.1.6 and 1.6.2
99 # Notation, Section 1.3.2
101 When destination register operands (`RT, RS`) are prefixed by a single
102 underscore (`_RT, _RS`) the variable also contains the contents of the
104 This avoids confusion in pseudocode when a destination register is
105 assigned (`RT <- x`) but earlier it was the operand bits that were
106 checked (`if RT = 0`)
112 [[!inline pages="openpower/sv/svstep" raw=yes ]]
113 [[!inline pages="openpower/sv/setvl" raw=yes ]]
114 [[!inline pages="openpower/sv/sprs" raw=yes ]]
122 Add the following to Book I, 1.6.1, SVL-Form
125 |0 |6 |11 |16 |23 |24 |25 |26 |31 |
126 | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
127 | PO | RT | / | SVi |/ |/ |vf | XO |Rc |
130 * Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
131 * Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
132 * Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
133 * Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
135 Add the following to Book I, 1.6.2
139 Field used in Simple-V to specify whether MVL (maxvl in the SVSTATE SPR)
143 Field used in Simple-V to specify whether "Vertical" Mode is set
144 (vfirst in the SVSTATE SPR)
147 Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
150 Simple-V immediate field used by setvl for setting VL or MVL
151 (vl, maxvl in the SVSTATE SPR)
152 and used as a "Mode of Operation" selector in svstep
158 Appendix E Power ISA sorted by opcode
159 Appendix F Power ISA sorted by version
160 Appendix G Power ISA sorted by Compliancy Subset
161 Appendix H Power ISA sorted by mnemonic
163 | Form | Book | Page | Version | mnemonic | Description |
164 |------|------|------|---------|----------|-------------|
165 | SVL | I | # | 3.0B | svstep | Vertical-First Stepping and status reporting |
166 | SVL | I | # | 3.0B | setvl | Cray-like establishment of Looping (Vector) context |