openpower/sv/rfc/ls010/trial_addi.mdwn

   1 # Example demonstration instruction modified to SVP64 (better)
   2
   3 <!-- hide -->
   4 Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
   5 <!-- show -->
   6
   7 The idea here is to review a modified version of a Power ISA 3
   8 instruction definition, to add SVP64 in a completely non-disruptive
   9 fashion.
  10
  11 The proposal is therefore to add a clear alternative "Operand namespace",
  12 which already has precedent from EXT1xx-Prefixed instructions.
  13
  14 **Assembler Syntax**
  15
  16 a danger of even declaring the existence "`sv.addi RT,RA,SI`" is the
  17 assumption that it is different from `addi RT,RA,SI`.  Alternative
  18 encodings that conflict with the Defined word-instruction (`addi`
  19 in this case) are flat-out **prohibited** in SVP64.
  20
  21 **Vector/Scalar Operands**
  22
  23 another danger - this one a permutation-explosion - exists when
  24 specifying which register operands are vector and which scalar:
  25 they all are, and they all are, independently of each other.
  26 this looks fine:
  27
  28 * `sv.addi RT,RA,SI`
  29 * `sv.addi RT,*RA,SI`
  30 * `sv.addi *RT,RA,SI`
  31 * `sv.addi *RT,*RA,SI`
  32
  33 but this gets massively out of hand very quickly:
  34
  35 * `sv.fmadds FRT,FRA,FRB,FRC`
  36 * ...
  37 * ...
  38 * `sv.fmadds *FRT,*FRA,*FRB,*FRC`
  39
  40 # SVP64-annotated addi instruction (prototype)
  41
  42 **Add Immediate** D-Form
  43
  44 * `addi RT,RA,SI`
  45
  46 ```
  47     Defined Word-instruction: D-Form
  48         |    14 |   RT            |    RA       |     SI       |
  49         | 0     | 6               | 11          | 16        31 |
  50 ```
  51
  52 * pseudocode.RA <- `D-Form.RA`
  53 * pseudocode.RT <- `D-Form.RT`
  54 * pseudocode.SI <- `D-Form.SI`
  55
  56 **Prefixed Add Immediate** MLS:D-form
  57
  58 * `paddi RT,RA,SI,R`
  59
  60 ```
  61     Prefix: MLS
  62         |    1  |   2    | 0 | // | R  | //  |     si0         |
  63         | 0     | 6      | 8 | 9  | 11 | 12  | 14           31 |
  64
  65     Suffix:: D-Form
  66         |    14 |   RT            |    RA       | si1          |
  67         | 0     | 6               | 11          | 16        31 |
  68 ```
  69 Operands:
  70
  71 * pseudocode.RA <- `D-Form.RA`
  72 * pseudocode.RT <- `D-Form.RT`
  73 * pseudocode.SI <- `MLS.si0 || MLS.si1`
  74
  75 **Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
  76
  77 * `sv.addi RT,RA,SI`
  78
  79 ```
  80     Prefix: SVP64-RM-1S1D/EXTRA3/Normal
  81         |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
  82         | 0     | 6      | 8         | 17    26 | 27        31 |
  83     Defined Word-instruction: D-Form
  84         |    14 |   RT            |    RA       |     SI       |
  85         | 0     | 6               | 11          | 16        31 |
  86 ```
  87
  88 Operands:
  89
  90 * pseudocode.RA <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[0:2])`
  91 * pseudocode.RT <- `SVP64_EXTRA3_DECODE(D-Form.RT, SVP64.RM.EXTRA[3:5])`
  92 * pseudocode.SI <- `D-Form.SI`
  93
  94 Pseudo-code:
  95
  96 ```
  97     if "addi" then
  98         RT <- (RA|0) + EXTS64(SI)
  99     if "paddi" & R=0 then
 100         RT <- (RA|0) + EXTS64(si0||si1)
 101     if "paddi" & R=1 then
 102         RT <- CIA + EXTS64(si0||si1)
 103
 104 ```
 105
 106 Special Registers Altered:
 107
 108 ```
 109     None
 110 ```
 111