openpower/sv/rfc/ls010/trial_addi.mdwn

   1 # Example demonstration instruction modified to SVP64 (better)
   2
   3 <!-- hide -->
   4 Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
   5 <!-- show -->
   6
   7 The idea here is to review a modified version of a Power ISA 3
   8 instruction definition, to add SVP64 in a completely non-disruptive
   9 fashion.
  10
  11 The proposal is therefore to add a clear alternative "Operand namespace",
  12 which already has precedent from EXT1xx-Prefixed instructions.
  13
  14
  15 # SVP64-annotated addi instruction (prototype)
  16
  17 **Add Immediate** D-Form
  18
  19 * `addi RT,RA,SI`
  20
  21 ```
  22     Defined Word-instruction:
  23         |    14 |   RT            |    RA       |     SI       |
  24         | 0     | 6               | 11          | 16        31 |
  25 ```
  26
  27 * pseudocode.RA <- `D-Form.RA`
  28 * pseudocode.RT <- `D-Form.RT`
  29 * pseudocode.SI <- `D-Form.SI`
  30
  31 **Prefixed Add Immediate** MLS:D-form
  32
  33 * `paddi RT,RA,SI,R`
  34
  35 ```
  36     Prefix:
  37         |    1  |   2    | 0 | // | R  | //  |     si0         |
  38         | 0     | 6      | 8 | 9  | 11 | 12  | 14           31 |
  39
  40     Suffix::
  41         |    14 |   RT            |    RA       | si1          |
  42         | 0     | 6               | 11          | 16        31 |
  43 ```
  44 Operands:
  45
  46 * pseudocode.RA <- `D-Form.RA`
  47 * pseudocode.RT <- `D-Form.RT`
  48 * pseudocode.SI <- `MLS.si0 || MLS.si1`
  49
  50 **Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
  51
  52 * `sv.addi RT,RA,SI`
  53
  54 ```
  55     Prefix:
  56         |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
  57         | 0     | 6      | 8         | 17    26 | 27        31 |
  58     Defined Word-instruction:
  59         |    14 |   RT            |    RA       |     SI       |
  60         | 0     | 6               | 11          | 16        31 |
  61 ```
  62
  63 Operands:
  64
  65 * pseudocode.RA <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[0:2])`
  66 * pseudocode.RT <- `SVP64_EXTRA3_DECODE(D-Form.RT, SVP64.RM.EXTRA[3:5])`
  67 * pseudocode.SI <- `D-Form.SI`
  68
  69 Pseudo-code:
  70
  71 ```
  72     if "addi" then
  73         RT <- (RA|0) + EXTS64(SI)
  74     if "paddi" & R=0 then
  75         RT <- (RA|0) + EXTS64(si0||si1)
  76     if "paddi" & R=1 then
  77         RT <- CIA + EXTS64(si0||si1)
  78
  79 ```
  80
  81 Special Registers Altered:
  82
  83 ```
  84     None
  85 ```
  86