openpower/sv/rfc/ls010.mdwn

   1 # RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
   2
   3 **URLs**:
   4
   5 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
   6 * <https://libre-soc.org/openpower/sv/>
   7 * <https://libre-soc.org/openpower/sv/rfc/ls010/>
   8 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
   9 * <https://git.openpower.foundation/isa/PowerISA/issues/64>
  10 * <https://git.openpower.foundation/isa/PowerISA/issues/121>
  11
  12 **Severity**: Major
  13
  14 **Status**: New
  15
  16 **Date**: 04 Apr 2023. v2 TODO
  17
  18 **Target**: v3.2B
  19
  20 **Source**: v3.0B
  21
  22 **Books and Section affected**:
  23
  24 ```
  25     New Book: new Zero-Overhead-Loop
  26     New Appendix, Zero-Overhead-Loop
  27 ```
  28
  29 **Summary**
  30
  31 ```
  32     Adds a Zero-Overhead-Loop Subsystem based on the Cray True-Scalable Vector concept
  33     in a RISC-paradigm fashion.  Total instructions added is six, plus Prefix format.
  34 ```
  35
  36 **Submitter**: Luke Leighton (Libre-SOC)
  37
  38 **Requester**: Libre-SOC
  39
  40 **Impact on processor**:
  41
  42 ```
  43     Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  44     subsystem that in simple low-end (Embedded) systems may be minimalistically
  45     and easily be implemented by inserting a new fully-independent Pipeline Stage
  46     in between Decode and Issue, with very little disruption, and in higher
  47     performance pre-existing Multi-Issue Out-of-Order systems seamlessly fits likewise
  48     to significantly boost performance.
  49 ```
  50
  51 **Impact on software**:
  52
  53 ```
  54     Requires support for new instructions in assembler, debuggers, and related tools.
  55     Dramatically reduces instructions. Requires introduction of term "High-Level Assembler"
  56 ```
  57
  58 **Keywords**:
  59
  60 ```
  61     Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
  62     True-Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
  63     Digital Signal Processing (DSP), High-level Assembler
  64 ```
  65
  66 **Motivation**
  67
  68 Just at the time when customers are asking for higher performance,
  69 the seductive lure of SIMD, as outlined in the sigarch "SIMD Considered
  70 Harmful" article is getting out of control and damaging the reputation
  71 of mainstream general-purpose ISAs that offer it.  A solution from
  72 50 years ago exists in the form of Cray-Style True-Scalable Vectors.
  73 However the usual way that True-Scalable Vector ISAs are done *also*
  74 adds more instructions and complexifies the ISA.  Simple-V takes a step
  75 back to a simpler era in computing from half a century ago: the Zilog
  76 Z80 CPIR and LDIR instructions, and the 8086 REP instruction, and brings
  77 them forward to Modern-day Computing.  The result is a huge reduction in
  78 programming complexity, and a strong base to project the Power ISA back
  79 to the world's most powerful Supercomputing ISA for at least the next two
  80 decades.
  81
  82 **Notes and Observations**:
  83
  84 Related RFCs are [[ls008]] for the two Management instructions `setvl`
  85 and `svstep`, and [ls009]] for the REMAP Subsystem. Also [[ls001]] is
  86 a Dependency as it introduces Primary Opcode 9 64-bit encoding. An
  87 additional RFC [[ls005]] introduced XLEN on which SVP64 is also critically
  88 dependent, for Element-width Overrides.
  89
  90 **Changes**
  91
  92 Add the following entries to:
  93
  94 * A new "Vector Looping" Book
  95 * New Vector-Looping Chapters
  96 * New Vector-Looping Appendices
  97
  98 [[!tag opf_rfc]]
  99
 100 --------
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