openpower/sv/rfc/ls010.mdwn

   1 # RFC ls010 Simple-V Zero-Overhead Loop Prefix Subsystem
   2
   3 **URLs**:
   4
   5 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
   6 * <https://libre-soc.org/openpower/sv/>
   7 * <https://libre-soc.org/openpower/sv/rfc/ls010/>
   8 * <https://bugs.libre-soc.org/show_bug.cgi?id=1056>
   9 * <https://git.openpower.foundation/isa/PowerISA/issues/64>
  10 * <https://git.openpower.foundation/isa/PowerISA/issues/122>
  11 * <https://libre-soc.org/openpower/sv/ls010/trial_addi/>
  12 * <https://libre-soc.org/openpower/sv/ls010/hypothetical_addi/>
  13
  14 **Severity**: Major
  15
  16 **Status**: New
  17
  18 **Date**: 04 Apr 2023. v2 TODO
  19
  20 **Target**: v3.2B
  21
  22 **Source**: v3.1B
  23
  24 **Books and Section affected**:
  25
  26 ```
  27     New Book: new Zero-Overhead-Loop
  28     New Appendix, Zero-Overhead-Loop
  29 ```
  30
  31 **Summary**
  32
  33 ```
  34     Adds a Zero-Overhead-Loop Subsystem based on the Cray True-Scalable Vector concept
  35     in a RISC-paradigm fashion. Total instructions six 5-bit XO, plus Prefix format (PO9).
  36 ```
  37
  38 **Submitter**: Luke Leighton (Libre-SOC)
  39
  40 **Requester**: Libre-SOC
  41
  42 **Impact on processor**:
  43
  44 ```
  45     Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
  46     subsystem that in simple low-end (Embedded) systems may be minimalistically
  47     and easily be implemented by inserting a new fully-independent Pipeline Stage
  48     in between Decode and Issue, with very little disruption, and in higher
  49     performance pre-existing Multi-Issue Out-of-Order systems seamlessly fits likewise
  50     to significantly boost performance.
  51 ```
  52
  53 **Impact on software**:
  54
  55 ```
  56     Requires support for new instructions in assembler, debuggers, and related tools.
  57     Dramatically reduces instructions. Requires introduction of term "High-Level Assembler"
  58 ```
  59
  60 **Keywords**:
  61
  62 ```
  63     Cray Supercomputing, Vectorization, Zero-Overhead-Loop-Control (ZOLC),
  64     True-Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
  65     Digital Signal Processing (DSP), High-level Assembler
  66 ```
  67
  68 **Motivation**
  69
  70 Just at the time when customers are asking for higher performance,
  71 the seductive lure of SIMD, as outlined in the sigarch "SIMD Considered
  72 Harmful" article, is getting out of control and damaging the reputation
  73 of mainstream general-purpose ISAs that offer it.  A solution from
  74 50 years ago exists in the form of Cray-Style True-Scalable Vectors.
  75 However the usual way that True-Scalable Vector ISAs are done *also*
  76 adds more instructions and complexifies the ISA.  Simple-V takes a step
  77 back to a simpler era in computing from half a century ago: the Zilog
  78 Z80 CPIR and LDIR instructions, and the 8086 REP instruction, and brings
  79 them forward to Modern-day Computing.  The result is a huge reduction in
  80 programming complexity, and a strong base to project the Power ISA back
  81 to the world's most powerful Supercomputing ISA for at least the next two
  82 decades.
  83
  84 **Notes and Observations**:
  85
  86 Related RFCs are [[ls008]] for the two Management instructions `setvl`
  87 and `svstep`, and [[ls009]] for the REMAP Subsystem. Also [[ls001]] is
  88 a Dependency as it introduces Primary Opcode 9 64-bit encoding. An
  89 additional RFC [[ls005.xlen]] introduced XLEN on which SVP64 is also critically
  90 dependent, for Element-width Overrides.
  91
  92 **Changes**
  93
  94 Add the following entries to:
  95
  96 * A new "Vector Looping" Book
  97 * New Vector-Looping Chapters
  98 * New Vector-Looping Appendices
  99
 100 [[!tag opf_rfc]]
 101
 102 --------
 103
 104 \newpage{}
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